SERIES PMC408 PCI MEZZANINE CARD 32-CHANNEL DIGITAL I/O MODULE
___________________________________________________________________________________________
- 6 -
Configuration Registers
The PCI specification requires software driven initialization and
configuration via the Configuration Address space. This PMC
module provides 256 bytes of configuration registers for this
purpose. The PMC408 contains the configuration registers, shown
in Table 3.1, to facilitate Plug-and-Play compatibility.
The Configuration Registers are accessed via the Configuration
Address and Data Ports. The most important Configuration
Registers are the Base Address Registers and the Interrupt Line
Register which must be read to determine the base address
assigned to the PMC408 and the interrupt request line that goes
active on a PMC408 interrupt request.
Table 3.1 Configuration Registers
Reg.
Num.
D31 D24
D23 D16
D15 D8
D7 D0
0
Device ID=464D
Vendor ID= 16D5
1
Status Command
2
Class Code=118000
Rev ID=00
3
BIST Header
Latency Cache
4
32-bit Memory Base Address for PMC408
4K-Byte Block
5 : 10
Not Used
11
Subsystem ID=0000
Subsystem Vendor
ID=0000
12
Not Used
13,14
Reserved
15
Max_Lat
Min_Gnt
Inter. Pin
Inter. Line
MEMORY MAP
This board is allocated a 4K byte block of memory that is
addressable in the PCI bus memory space to control the ON/OFF
states of individual low-side switches and/or the acquisition of digital
inputs from the field.
The memory space address map for the PMC408 is shown in
Table 3.2. Note that the base address for the PMC408 in memory
space must be added to the addresses shown to properly access
the PMC408 registers. Register accesses as 32, 16, and 8-bit data
in memory space are permitted. All the registers of the PMC408 are
accessed via data lines D0 to D15. The most significant word of a
32-bit access is not used by the PMC408. A 32-bit read will return
logic “0” for the most significant word
Table 3.2: PMC408 I/O Space Address Memory Map
Hex
Base
Addr.+
MSB
D15 D08
LSB
D07 D00
Hex
Base
Addr.+
001
INTERRUPT REGISTER
000
201
READ- Digital Input
Channel Register A
CH15
↔
CH08
READ- Digital Input
Channel Register A
CH07
↔
CH00
200
205
READ- Digital Input
Channel Register B
CH31
↔
CH24
READ- Digital Input
Channel Register B
CH23
↔
CH16
204
209
R/W -Digital Output
Channel Register A
CH15
↔
CH08
R/W -Digital Output
Channel Register A
CH07
↔
CH00
208
20D
R/W - Digital Output
Channel Register B
CH31
↔
CH24
R/W -Digital Output
Channel Register B
CH23
↔
CH16
20C
211
NOT DRIVEN
1
R/W - Interrupt
Enable Register
1
CH07
↔
CH00
210
215
NOT DRIVEN
1
R/W -Interrupt Type
Config. Register
1
CH07
↔
CH00
214
219
NOT DRIVEN
1
R/W - Interrupt
Polarity Register
1
CH07
↔
CH00
218
21D
NOT DRIVEN
1
R/W - Interrupt
Status Register
1
CH07
↔
CH00
21C
221
NOT DRIVEN
1
NOT USED
2
220
225
↓
2FD
NOT USED
2
224
↓
2FC
Notes (Table 3.2):
1. Bits 15-8 of these registers are not used. Bits 15-8 will be driven
high (1’s).
2. The PMC408 will respond to addresses that are "Not Used".
Interrupt Register, (Read/Write) - (Base + 000H)
This read/write register is used to: enable board interrupt,
determine the pending status of interrupts, and release an interrupt.
The function of each of the interrupt register bits are described
in Table 3.3. This register can be read or written with either 8-bit,
16-bit, or 32-bit data transfers. A power-up or system reset sets all
interrupt register bits to 0.
Table 3.3: Interupt Register
BIT FUNCTION
0
Board Interrupt Enable Bit. This bit must be set to
logic “1” to enable generation of interrupts from the
PMC module. Setting this bit to logic “0” will disable
board interrupts. (Read/Write Bit)
1
Interrupt Pending Status Bit. This bit can be read to
determine the interrupt pending status of the PMC
module. When this bit is logic “1” an interrupt is
pending and will cause an interrupt request if bit-0 of
the register is set. When this bit is a logic “0” an
interrupt is not being requested.
7 to 2
Not Used
1
8
Software Reset
Writing a logic “1” to this bit will cause a reset of PMC
module. Bit-0 of this register will not be affected.
15 to 9
Not Used
1
Notes (Table 3.3):
1. All bits labeled “Not Used” will return logic “0” when read.
Digital Input Registers A & B (Read Only)
When the Digital Input Channel Data Registers are read, the
value read corresponds to the actual state of the input channels at
the time of the read. If the channel’s tandem output mosfet is being
controlled and its drain is loaded, then reading the digital input
channel data register will return the state of the output (it is directly
connected to the drain). This is an efficient method of
