SERIES IP22O INDUSTRIAL I/O PACK
1
2
-BIT HIGH-DENSITY ANALOG OUTPUT MODULE
•
CAUTION: POWER MUST BE TURNED OFF BEFORE
REMOVING OR INSERTING BOARDS
Acromag's Applications Engineers can provide further technical
assistance if required. When needed, complete repair services are
also available from Acromag.
6.0 SPECIFICATIONS
GENERAL SPECIFICATIONS
Operating Temperature0
to +70°C
- 4 0 ° C to +85°C (E Versions)
Relative Humidity5
-
9
5
%
Non-Condensing
Storage Temperature-
5
5
°
C
to +100°C
Physical ConfigurationS i n g l e Industrial I/O Pack Module
Length3
.
9
0
0
in. (99.0 mm)
Width1
.
8
0
0
in. (45.7 mm)
Board Thickness0
.
0
6
2
in. (1.59 mm)
Max Component Height0 . 3 1 4 in. (7.97 mm)
Connectors:
P1 (IP Logic Interface)5
0
-pin female receptacle header
(AMP 173279-3 or equivalent).
P2 (Field I/O)5
0
-pin female receptacle header
(AMP 173279-3 or equivalent).
Power:
+5 Volts (±5%)1
5
0
m
A
Typical,
200mA Maximum.
+12 Volts (±5%) from P1 or 200mA Typical, 300mA Maximum
+15 Volts (±5%) from P2( S e e Notes 1 & 2 Below)
-12 Volts (±5%) from P1 or8 0 m A Typical, 180mA Maximum
-15 Volts (±5%) from P2( S e e Notes 1 & 2 Below)
Non-IsolatedL
o
g
i
c
and field commons have a
direct electrical connection.
Notes (Power):
1. The ±12 volt power supplies are normally supplied through P1
(logic interface connector). Optionally (jumper selectable on the
IP), the user may connect external ±15 volt supplies through the
field I/O interface connector, P2.
2. The maximum current draw assumes that the rated current of
5mA per channel is drawn. Current draw will be reduced
proportionately for high impedance output loads.
ANALOG OUTPUTS
Output Channels (Field Access)I P 2 2 0 - 1 6 : 16 Single-Ended.
IP220-8: 8 Single-Ended.
Voltage (Non-Isolated).
Bipolar -10V to +10V (See Notes
3 & 4).
Output Current-
5
m
A
to +5mA (Maximum); this
corresponds to a minimum load
resistance of 21<12 with a 10V
output (See Notes 3 & 4).
Data Format (left-justified)B i p o l a r Offset Binary (BOB).
DAC Programming
I m m e d i a t e (transparently
programmed to DAC output);
Simultaneous (input latches of
multiple DAC's are loaded with
new data before simultaneously
updating DAC outputs).
Resolution1
2
-bits.
Monotonicity over Temperature1 2 -bits.
Linearity Error±
1/2 LSB (Maximum).
Differential Linearity Error±
1 LSB (Maximum).
Output Type
Output Range
System Accuracy + 0 . 0 2 5 % of 20V SPAN
Maximum corrected error (i.e.
calibrated) at 25°C (See Note 5)
with the output unloaded.
Settling Time8
u
S
to within 0.012% for a 20V
step change (load of 5KLI in
parallel with 470 pf).
Output at ResetB
i
p
o
l
a
r
Zero Volts (See Note 6).
Output Noise2
m
V
rms in a 20MHz
bandwidth, Typical.
Output Impedence1
0
Maximum at 25°C (a load of
101q1 will introduce 0.01%
output error).
Short Circuit ProtectionI n d e f i n i t e a t 25°C.
Output Load StabilityM a x i m u m recommended
capacitive load is 500pf.
Capacitive loads above 500pf
can be tolerated, but with
additional overshoot.
Gain Drift±
3
0
p
p
m
/
p
e
r
°C Maximum.
Bipolar Zero Drift (M 1 5 p p m of 20V SPAN per °C.
Resistance to RFIE
r
r
o
r
is < ± 0.25% of a 20V
span for RFI field strengths up
to 10V/m at 27MHz, 159MHz,
and 460MHz.
Notes (Analog Outputs):
3. Maximum output current (±5mA) can be achieved at the range
endpoints using the internal ±12 volt power supplies sourced
through P1. The external ±15 volt power supplies, sourced
through P2, are not required to achieve rated output.
4. The actual outputs may fall short of the range endpoints due to
hardware offset and gain errors. The software calibration
corrects for these across the output range, but cannot extend
the output beyond that achievable with the hardware.
5. Offset and gain calibration coefficients stored in the ID PROM
must be used to perform software calibration in order to achieve
the specified accuracy. Specified accuracy does not include
quantization error. Follow the output connection
recommendations of Section 2, because non-ideal grounds can
degrade overall system accuracy.
6. The reset function resets only the D/A (i.e. output) latch of the
input double buffer. Therefore, after a reset, good data must be
written to all the input latches before a simultaneous DAC output
update. Otherwise, old data or unknown data present in the
input latches will be transferred to the D/A output latch,
producing an undesired analog output.
INDUSTRIAL I/O PACK COMPLIANCE
SpecificationT
h
i
s
module meets or exceeds
all written Industrial I/O Pack
specifications for Type I
modules per ANSINITA 4-1995.
Electrical/Mechanical InterfaceS i n g l e -Size IP Module.
IP Data Transfer Cycle Types Supported:
Input/Output (IOSel°)1
6
-bit word write of 12-bit left-
justified channel data; 16-bit
write to control registers; 16-bit
read of 8-bit right-justified DAC
offset and gain calibration
coefficients.
ID Read (IDSeI*)3
2
x
8
ID PROM read on DO..D7.
