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INDUSTRIAL I/O PACK SERIES AVME9675A

VME64x bus 6U CARRIER BOARD

Acromag, Inc. Tel: 248-295-0310

- 40 - http://www.acromag.com

- 40 -

https://www.acromag.com

The VME64x bus interface is implemented in the logic of the

carrier board’s

Field Programmable Gate-Array (FPGA). The FPGA implements VME64x bus
specification ANSI/VITA 1-1994 (VME64) & ANSI/VITA 1.1-1997 (VME64x) as
an interrupting slave including the following data transfer types.

*

A24, D16/D08(O) CR/CSR Register Space

*

A16, D16/D08(O) Carrier Register Short I/O Access

*

A16, D16/D08(O) IP Module ID Space

*

A16, D16/D08(EO) IP Module I/O Space

*

A24, D16/D08(EO) IP Module Memory Space

The carrier board’s VME64x bus data tra

nsfer rates are typically:

•

450ns for accesses to the carrier board registers.

•

450ns for data transfers to the IP modules (assuming 0 wait states on
IP).

The c

arrier board’s FPGA monitors the six geographical address signal inputs

supplied by the VME64x backplane on the P1 connector.  These signals
determine the base address of the carrier in the standard (A24)
Configuration ROM / Control & Status Register (CR/CSR) address space.  The
host computer must scan the CR/CSR space to determine active card
locations within the VME64x chassis.  When the CR/CSR address matches

the card’s, the FPGA controls and implements the required bus transfer

allowing communication wi

th the card’s CR/CSR space.

4.3 Carrier Board Registers

The carrier board registers (presented in section 3) are implemented in the

logic of the carrier board’s FPGA. An outline of the functions provided by

the carrier board registers includes:

•

Configuration ROM (CR within CR/CSR space)

registers provide carrier

board identification and capabilities information.

•

Control & Status Registers (CSR within CR/CSR space)

allow the base

address of the Short (A16) I/O carrier space to be relocated on 1K byte
boundaries as desired by the host computer using the

Function 0

Address DEcoder CompaRe (ADER)

register and accesses to this space

to be enabled or disabled using the

Bit Set or Bit Clear Registers

.

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Summary of Contents for AVME9675A Series

Page 1: ...nt Carrier Boards USER S MANUAL ACROMAG INCORPORATED 30765 South Wixom Road Wixom MI 48393 2417 U S A Tel 248 295 0310 Email solutions acromag com Copyright 2020 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8501171A ...

Page 2: ...ring Information 6 1 3 2 Key Features 6 1 3 3 Key Features VME64x bus Interface 7 1 4 Signal Interface Products 8 1 5 Software Support 9 Windows 9 VxWorks 10 Linux 10 2 0 PREPARATION FOR USE 11 2 1 Unpacking and Inspecting 11 2 2 Card Cage Considerations 12 2 3 Board Configuration 12 2 4 VMEbus Interface Configuration 12 2 5 Address Decode Jumper Configuration 13 Table 2 1 Geographical Address Pin...

Page 3: ...Registers 25 3 1 Identification ROM Read Only 32 Odd Byte Addresses 27 Table 3 3 Generic IP Module ID Space Identification ID ROM 28 3 2 Carrier Board Status Register Read Write Base C1H 28 3 3 Interrupt Level Register Read Write Base C3H 30 3 4 IP Error Register Read Base C5H 31 3 5 IP Memory Enable Register Read Write Base C7H 31 3 6 IP Memory Base Address Size Register Read Write 32 IP_A Base D...

Page 4: ...Y OF OPERATION 39 4 1 CARRIER BOARD OVERVIEW 39 4 2 VME64x bus Interface 39 4 3 Carrier Board Registers 40 4 4 IP Logic Interface 41 4 5 Carrier Board Clock Circuitry 42 4 6 IP Read and Write Cycle Timing 43 4 7 VME64x Bus Interrupter 44 4 8 Power Failure Monitor 45 4 9 Access LEDs and Pulse Stretcher Circuitry 45 4 10 Power Supply Filters 45 4 11 Power Supply Fuses 45 5 0 SERVICE AND REPAIR 46 5 ...

Page 5: ...ion 49 Table 6 4 1 AVME9675A 49 6 5 INDUSTRIAL I O PACK COMPLIANCE 49 6 6 VME64x bus COMPLIANCE 50 APPENDIX 51 CABLE MODEL 5028 187 SCSI 2 to Flat Ribbon Shielded 51 Termination Panel Model 5025 552 51 VME64x TRANSITION MODULE MODEL TRANS 200 52 DRAWINGS 53 4501 800 AVME9675A IP Locations 53 4501 801 Mechanical Assembly Drawing 53 4501 802 AVME9675A Block Diagram 55 4501 758 Cable SCSI 2 to Flat R...

Page 6: ...ed in any form without the prior written consent of Acromag 1 2 1 Trademark Trade Name and Copyright Information 2017 by Acromag Incorporated All rights reserved Acromag and Xembedded are registered trademarks of Acromag Incorporated All other trademarks registered trademarks trade names and service marks are the property of their respective owners 1 2 2 Class A Product Warning This is a Class A p...

Page 7: ...our industry standard IP modules IP Modules are available from Acromag and other vendors in a wide variety of Input Output configurations to meet the needs of varied applications Provides Full IP Data Access Supports accesses to IP input output memory identification data and interrupt spaces Full IP Register Access Makes maximum use of logically organized programmable registers on the carrier boar...

Page 8: ...supervisor circuit provides power on power off and low power detection reset signals to the IP modules per the IP specification Individually Filtered Power Filtered 5V 12V and 12V DC power is provided to the IP modules via passive filters present on each supply line serving each IP This provides optimum filtering and isolation between the IP modules and the carrier board and allows analog signals ...

Page 9: ...ify write cycles Interrupt Support I 1 7 interrupter D16 D08 O Up to two interrupt requests are supported for each IP module The VME64x bus interrupt level is software programmable Carrier board software programmable registers are utilized as interrupt request control and status monitors Interrupt release mechanism is Release On Register Access RORA type 1 4 Signal Interface Products See Appendix ...

Page 10: ...odule with front panel hardware adhering to the VME64x bus mechanical dimensions and IEEE Standard 1101 11 1998 with a printed circuit board depth of 80mm which is a standard transition module depth The transition module connects to Acromag Termination Panel Model 5025 552 using SCSI 2 to Flat Ribbon Cable Shielded Model 5028 187 to the rear of the card cage and to AVME9670 AVME9675A 2 AVME9675A 4...

Page 11: ...raries for all Industry Pack modules The software is implemented as a library of C functions which link with existing user code to make possible simple control of all Acromag Industry Pack modules Linux Acromag provides a software product consisting of Linux software This software Model IPSW API LNX is composed of Linux libraries for all Industry Pack modules The software is implemented as a libra...

Page 12: ...electromagnetic magnetic or radioactive fields unless the device is contained within its original manufacturer s packaging Be aware that failure to comply with these guidelines will void the Acromag Limited Warranty 2 1 Unpacking and Inspecting Upon receipt of this product inspect the shipping carton for evidence of mishandling during transit If the shipping carton is badly damaged or water staine...

Page 13: ... the following Sections The jumper locations and IP module positions are shown in Figure 2 Drawing 5044 452 Power should be removed from the board when installing IP modules cables termination panels and field wiring Refer to Mechanical Assembly Figure 3 Drawing 4501 434 and your IP module documentation for specific configuration and assembly instructions 2 4 VMEbus Interface Configuration The car...

Page 14: ...mmunication with the carrier must be made to the CR CSR space using geographic addressing per the VME64x specification The VME64x backplane applies six geographic address signal lines to the P1 connector as listed in Table 2 1 Table 2 1 Geographical Address Pin Assignments Slot No GAP Pin GA4 Pin GA3 Pin GA2 Pin GA1 Pin GA0 Pin 1 Open Open Open Open Open GND 2 Open Open Open Open GND Open 3 GND Op...

Page 15: ...n of the space Following power up accesses to the card s Short I O A16 space are disabled The base address of the carrier in the Short I O space and the desired address modifier must be programmed using the Function 0 Address DEcoder CompaRe ADER Register in the Control Status Register CSR portion of the CR CSR space Then accesses to the Short I O space can be enabled by writing to the Bit Set Reg...

Page 16: ...ns A D respectively IP module assignment is marked on the transition module for easy identification see IP location drawing 4501 800 for physical locations of the IP modules SCSI 2 Round cable assemblies and Acromag termination panels or user defined terminations can be quickly mated to the transition module connectors Pin assignments are defined by the IP I O Mapping to VME64x Standard ANSI VITA ...

Page 17: ...2 P13 and P14 respectively on the carrier board IP location is silk screened on the board for easy identification Field and logic side connectors are keyed to avoid incorrect assembly P11 P12 P13 and P14 are 50 pin male plug header connectors These AMP 173280 3 connectors mate to AMP 173279 3 connectors or similar on the IP modules This provides excellent connection integrity and utilizes gold pla...

Page 18: ... by the carrier board 2 11 VMEbus Connections Table 2 3 indicates the pin assignments for the VME64x bus signals at the P1 connector The P1 connector is the upper rear connector on the AVME9675A board as viewed from the front The connector consists of 32 rows of five pins labeled A B C D and Z Pin Z1 is located at the upper right hand corner of the connector if the board is viewed from the front c...

Page 19: ...3 RsvBus AM4 GND A15 RsvBus 24 GND A07 IRQ7 A14 3 3V 25 RsvBus A06 IRQ6 A13 RsvBus 26 GND A05 IRQ5 A12 3 3V 27 RsvBus A04 IRQ4 A11 LI I 28 GND A03 IRQ3 A10 3 3V 29 RsvBus A02 IRQ2 A09 LI O 30 GND A01 IRQ1 A08 3 3V 31 RsvBus 12V 5VSTDBY 12V GND 32 GND 5V 5V 5V VPC Asterisk is used to indicate an active low signal Shaded area are pins defined under the VME64 bus specification BOLD ITALIC Logic Lines...

Page 20: ... 13 B14 A15 Not Used A16 B15 14 GND A17 Not Used A18 B16 15 B17 A19 Not Used A20 B18 16 GND A21 Not Used A22 B19 17 B20 A23 Not Used A24 B21 18 GND A25 Not Used A26 B22 19 B23 A27 Not Used A28 B24 20 GND A29 Not Used A30 B25 21 B26 A31 Not Used A32 B27 22 GND A33 Not Used A34 B28 23 B29 A35 Not Used A36 B30 24 GND A37 Not Used A38 B31 25 B32 A39 Not Used A40 B33 26 GND A41 Not Used A42 B34 27 B35 ...

Page 21: ... P2 connector are mapped per the IP Module I O to VME64x bus Standard ANSI VITA 4 1 1996 Refer to this standard for additional information on the VME64x bus signals Pin Row A Row B Row C Row D Row E Row F 1 D1 D2 D3 D4 D5 GND 2 D6 D7 D8 D9 D10 NP 3 D11 D12 D13 D14 D15 GND 4 D16 D17 D18 D19 D20 NP 5 D21 D22 D23 D24 D25 GND 6 D26 D27 D28 D29 D30 NP 7 D31 D32 D33 D34 D35 GND 8 D36 D37 D38 D39 D40 NP ...

Page 22: ... PROM to initialize the logic circuitry for normal operation This time is measured as the first 145mS typical after the 5 Volt supply rises to 2 5 Volts at power up The VME64x bus specification requires that the bus master drive the system reset for the first 200mS after power up thus inhibiting any data transfers from taking place IP control registers are also reset following a power up sequence ...

Page 23: ...considered non isolated since there is electrical continuity between the VME64x bus and the IP grounds Therefore unless isolation is provided on the IP module itself the field I O connections are not isolated from the VME64x bus Care should be taken in designing installations without isolation to avoid ground loops and noise pickup This is particularly important for analog I O applications when a ...

Page 24: ...o 0x7FFFF The AVME9675 s position in the CR CSR Space array is determined by the CR CSR Base Address Register CR CSR BAR The AVME9675A uses the VME64x Geographical Addressing method to automatically provide the CR CSR BAR value Table 3 1 AVME9675A Carrier Board Short I O Memory Map Base Address Hex EVEN Byte D15 D08 ODD Byte D07 D00 Base Address Hex 0000 007E IP A I O Space High Byte IP A I O Spac...

Page 25: ... Input Output IO and Identification ID spaces of each IP are accessible via the VMEbus Short I O space as shown in Table 3 1 The carrier board may optionally occupy memory in the VMEbus standard A24 address space if needed for IP modules containing Memory space IP memory will only be mapped into the standard memory space if it is enabled for a particular IP per the user programmable IP Memory Enab...

Page 26: ...d Carrier Board Status Register 00C1 00C2 Not Used Interrupt Level Register 00C3 00C4 Not Used IP Error Register 00C5 00C6 Not Used IP Memory Enable Register 00C7 00C8 00CE Not Used Not Used 00C9 00CF 00D0 Not Used IP A Memory Base Address Size Register 00D1 00D2 Not Used IP B Memory Base Address Size Register 00D3 00D4 Not Used IP C Memory Base Address Size Register 00D5 00D6 Not Used IP D Memory...

Page 27: ...ble Register 00E1 00E2 Not Used IP Interrupt Pending Register 00E3 00E4 Not Used IP Interrupt Clear Register 00E5 00E6 00EE Not Used Not Used 00E7 00EF 00F0 Firmware Revision 00F1 00F2 Flash Data Reserved 00F3 00F4 Flash Chip Select Reserved 00F5 00F6 Not Used 00F7 00F8 XADC Status Control Register 00F9 00FA XADC Address Register 00FB 00FB 00FE Not Used Not Used 00FC 00FF ...

Page 28: ...ID ROM Format I Both fixed and variable information may be present within the ID ROM Fixed information includes the IPAC identifier model number and manufacturer s identification codes Variable information may include unique information required for the module The identification Section for each IP module is located in the carrier board memory map per Table 3 3A ID bytes are addressed using only t...

Page 29: ...1 07 C 43 09 A3 Acromag ID Code 0B mm IP Model Code1 0D 00 Not Used Revision 0F 00 Reserved 11 00 Not Used Driver ID Low Byte 13 00 Not Used Driver ID High Byte 15 nn Total Number of ID PROM Bytes 17 cc CRC 19 to 2 nn 1 xx IP Specific Space 2 nn 1 to 3F yy Not Used Notes Table 3 3 1 The IP model number is represented by a two digit code within the ID ROM e g the IP405 model is represented by 01 He...

Page 30: ...can result in a bus error due to time out When this bit is set to 0 automatic acknowledgement is enabled The carrier will acknowledge the access even if the IP module does not or if there is no IP module present Bit 5 of this register will be set to indicate that the last IP module access has timed out Bit 5 Timed Out Access This bit when set to 1 indicates that the last IP module has timed out Th...

Page 31: ...of IP interrupt requests to the desired VME64x bus interrupt level Note that the Global Interrupt Enable bit in the Carrier Board Status Register must be set for interrupts to be enabled from the carrier board Also the specific IP interrupt request must be enabled via its corresponding bit in the Interrupt Enable Register described subsequently MSB D7 D6 D5 D4 D3 D2 D1 LSB D0 Not Used Not Used Not...

Page 32: ...l 0 if read Bit 0 IP Error Read This bit will be a 1 when any IP module asserts its Error signal This bit will be 0 when there is no error Reset Condition Bit will be 0 no error unless driven by IP 3 5 IP Memory Enable Register Read Write Base C7H The IP Memory Enable Register allows the user to program which IP modules will be accessible in the standard A24 memory space An enable bit is associate...

Page 33: ...et Condition Set to 0 memory space accesses disabled for IP A 3 6 IP Memory Base Address Size Register Read Write IP_A Base D1H IP_B Base D3H IP_C Base D5H IP_D Base D7H The IP Memory Base Address Size Registers are user programmable to define the starting address of standard A24 memory space and the size of that memory space corresponding to IP modules A through D The memory size for each enabled...

Page 34: ...obal Interrupt Enable bit in the Carrier Board Status Register must be set for interrupts to be enabled from the carrier board The user must also configure the VME64x bus interrupt level using the Interrupt Level Register MSB D7 D6 D5 D4 D3 D2 D1 LSB D0 IP D Int1 Ena IP D Int0 Ena IP C Int1 Ena IP C Int0 Ena IP B Int1 Ena IP B Int0 Ena IP A Int1 Ena IP A Int0 Ena Where All Bits IP Interrupt Enable...

Page 35: ...on Set to 0 3 9 IP Interrupt Clear Register Write Base E5H The IP Interrupt Clear Register is used to individually clear the IP interrupt Pending bits set in the IP Interrupt Pending register MSB D7 D6 D5 D4 D3 D2 D1 LSB D0 IP D Int1 Clear IP D Int0 Clear IP C Int1 Clear IP C Int0 Clear IP B Int1 Clear IP B Int0 Clear IP A Int1 Clear IP A Int0 Clear Where All Bits IP Interrupt Clear Write Writing ...

Page 36: ... bits digitized and output from the ADC can be converted to temperature by using the following equation 15 273 1024 975 503 ADCcode C e Temperatur The 10 bits digitized and output from the ADC can be converted to voltage by using the following equation V ADCcode volts age SupplyVolt 3 1024 XADC Address Register Read Write Base FBH This read write register is used to set the XADC address register w...

Page 37: ...uccessful communication with each of up to four IP modules A D These LED s are driven by the corresponding IP acknowledge signal which is lengthened by the logic in the FPGA on the carrier board to make the access visible to the user This means that frequent accesses to an IP will result in constant LED illumination The LED s indicate I O memory interrupt acknowledge and ID space accesses Note tha...

Page 38: ...ram the desired interrupt level per bits 2 1 0 4 Write 1 to the IP Interrupt Clear Register corresponding to the desired IP interrupt request s being configured 5 Write 1 to the IP Interrupt Enable Register bits corresponding to the IP interrupt request to be enabled 6 Enable interrupts from the carrier board by writing a 1 to bit 3 global interrupt enable bit in the Carrier Board Status Register ...

Page 39: ...t in the IP Interrupt Enable Register B Take any IP specific action required to remove the interrupt request at its source C Clear the interrupting IP by writing a 1 to the appropriate bit in the IP Interrupt Clear Register D Enable the interrupting IP by writing a 1 to the appropriate bit in the IP Interrupt Enable Register 8 If the IP interrupt stimulus has been removed and no other IP modules h...

Page 40: ...tion module TRANS 200 to the Termination Panel At the Termination Panel field I O signals are connected to a 50 position terminal block via screw clamps The AVME9675A contains up to four IP modules and thus 200 I O connections may be provided via the transition module through SCSI 2 connectors marked A D The TRANS 200 was originally designed for use with the AVME9670 product which supports four IP...

Page 41: ...64x backplane on the P1 connector These signals determine the base address of the carrier in the standard A24 Configuration ROM Control Status Register CR CSR address space The host computer must scan the CR CSR space to determine active card locations within the VME64x chassis When the CR CSR address matches the card s the FPGA controls and implements the required bus transfer allowing communicat...

Page 42: ...upt Level Register and pending interrupts can be monitored and cleared via carrier registers IP Interrupt Pending and IP Interrupt Clear Registers Lastly pending interrupts can be globally monitored and released to the VME64x bus via the Status Register 4 4 IP Logic Interface The IP logic interface is also implemented within the carrier board s FPGA The carrier board implements ANSI VITA 4 1995 fo...

Page 43: ... acromag com programmable VME64x bus interrupt levels 4 5 Carrier Board Clock Circuitry Separate 8MHz IP clocks are driven to each IP module All clock lines include series damping resistors to reduce clock overshoot and undershoot and similar length PC board trace lengths are employed to minimize clock skew between the IP modules ...

Page 44: ... are then synchronized to the IP 8MHz clock as required by the IP module specification Thus typically one 8MHz clock cycle later an IP select line goes active IOSEL IDSEL MEMSEL or INTSEL and is held active for one clock cycle With no IP wait states an active IP Acknowledge ACK signal is driven by the IP on the next rising edge of the 8MHz clock The carrier board samples ACK one clock cycle later ...

Page 45: ...tails The carrier board releases the interrupt to the VME64x bus by asserting the interrupt request level as pre programmed in the carrier s Interrupt Level Register The carrier board s interrupt logic then monitors the VME64x bus Interrupt Acknowledge Input IACKIN signal An active IACKIN signal detected by the carrier board is either passed to Interrupt Acknowledge Output IACKOUT or consumed by t...

Page 46: ...edged data transfer activates the pulse stretcher circuit The pulse stretcher s circuit is programmed to illuminate the LED for a duration of 0 125 seconds typical 4 10 Power Supply Filters Power line filters are dedicated to each IP module for filtering of the 5 12 and 12 volt supplies The power line filters are a T type filter circuit comprising ferrite bead inductors and a feed thru capacitor T...

Page 47: ... correctly configured Replacement of the carrier and or IP with one that is known to work correctly is a good technique to isolate a faulty board In order to perform accesses to the carrier and IP module in the A16 short space the A16 base address must be configured first within the CR CSR space and the module enabled The CR CSR space s base address is derived from geographical addressing signals ...

Page 48: ...tion of the installed IP modules This specification lists currents for the carrier boards only The carrier boards individually filter and provide 5V 12V and 12V power to each IP from the VME64x bus Note that the VME64x bus standard does not support 15V and 15V supplies but the carrier boards are designed to handle these if needed for unique situations The power supply filters are typically capable...

Page 49: ...mperature 55 to 100 C Summarized below are the expected current draws for each of the specified power supply voltages Power Supply Voltage Current Draw 5 0 VDC 5 0 233 A Typical 0 275 A maximum 12 VDC 5 Not Used 12 VDC 5 Not Used Non Isolated VMEbus and IP module logic commons have a direct electrical connection As such unless the IP module provides isolation between the logic and field side the f...

Page 50: ...ollowing two conditions 1 This device may not cause harmful interference and 2 this device must accept any interference received including interference that may cause undesired operation 6 4 Reliability Prediction Table 6 4 1 AVME9675A MTBF Mean Time Between Failure MTBF in hours using MIL HDBK 217F FN2 Per MIL HDBK 217 Ground Benign Controlled GBGC Temperature MTBF Hours MTBF Years Failure Rate F...

Page 51: ...ck VME64x bus Address Modifier Codes Short I O Space Base address is hardware jumper selectable Occupies 1K byte Responds to both address modifiers 29H 2DH in the VMEbus short I O space for carrier board registers and IP I O and ID PROM spaces Standard Address Space Responds to both address modifiers 39H 3DH in the VMEbus standard address space when such accesses to IP memory are enabled via progr...

Page 52: ...tor with backshell and spring latch hardware Other End IDC 50 pin female connector with strain relief Keying The SCSI 2 connector has a D Shell and the IDC connector has a polarizing key to prevent improper installation Shipping Weight 1 0 pound 0 5Kg packed Termination Panel Model 5025 552 Type Termination Panel For AVME967xA Boards Application To connect field I O signals to the Industrial I O P...

Page 53: ...101 11 1998 for 80 mm depth Connects to Acromag termination panel 5025 552 from the rear of the card cage and to AVME9670 AVME9675A boards within card cage via connectors RP0 and RP2 Schematic and Physical Attributes See Drawing 4501 760 Field Wiring Four SCSI 2 50 pin female connectors AMP 787082 5 or equivalent employing latch blocks and 30 micron gold in the mating area per MIL G 45204 Type II ...

Page 54: ...INDUSTRIAL I O PACK SERIES AVME9675A VMEx64 bus 6U CARRIER BOARD Acromag Inc Tel 248 295 0310 53 http www acromag com 53 https www acromag com Drawings 4501 800 AVME9675A IP Locations 4501 800A ...

Page 55: ...INDUSTRIAL I O PACK SERIES AVME9675A VME64x bus 6U CARRIER BOARD Acromag Inc Tel 248 295 0310 54 http www acromag com 54 https www acromag com 4501 801 Mechanical Assembly Drawing 4501 801A ...

Page 56: ...INDUSTRIAL I O PACK SERIES AVME9675A VMEx64 bus 6U CARRIER BOARD Acromag Inc Tel 248 295 0310 55 http www acromag com 55 https www acromag com 4501 802 AVME9675A Block Diagram 4501 802A ...

Page 57: ...INDUSTRIAL I O PACK SERIES AVME9675A VME64x bus 6U CARRIER BOARD Acromag Inc Tel 248 295 0310 56 http www acromag com 56 https www acromag com 4501 758 Cable SCSI 2 to Flat Ribbon 5028 187 ...

Page 58: ...INDUSTRIAL I O PACK SERIES AVME9675A VMEx64 bus 6U CARRIER BOARD Acromag Inc Tel 248 295 0310 57 http www acromag com 57 https www acromag com 4501 464 Termination Panel 5025 552 4501 464A 4501 464A ...

Page 59: ...INDUSTRIAL I O PACK SERIES AVME9675A VME64x bus 6U CARRIER BOARD Acromag Inc Tel 248 295 0310 58 http www acromag com 58 https www acromag com 4501 760 VME64x Transition Mod TRANS 200 4501 760B ...

Page 60: ...ic blocks and RAM blocks Process to Sanitize Power Down Type SRAM SDRAM etc Size User Modifiable Yes No Function Process to Sanitize Non Volatile Memory Does this product contain Non Volatile memory i e Memory of whose contents is retained when power is removed Yes No Type EEPROM Flash etc Flash Size 128 Meg x 1bit User Modifiable Yes No Function Data storage for FPGA Process to Sanitize Erase usi...

Page 61: ...OARD Acromag Inc Tel 248 295 0310 60 http www acromag com 60 https www acromag com Revision History The revision history for this document is summarized in the table below Release Date Version EGR DOC Description of Revision 25 SEP 2020 A GJB AMM Initial Release ...

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