Acromag AVME9670A Series User Manual Download Page 34 | Manualshive

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INDUSTRIAL I/O PACK SERIES
AVME9675A

VMEx64 bus 6U CARRIER BOARD

Acromag, Inc. Tel: 248-295-0310

- 33 -

http://www.acromag.com

- 33 -

https://ww.acromag.com

firmware is at revision A then this register will read 0x41 in the least
significant byte or B= 0x42, C=0x43, etc.

XADC Status/Control Register (Read/Write) - Base + F9H

This read/write register will access the XADC register at the address set in
the XADC Address Register.

For example, the address of the XADC Status register that is to be accessed
is first set via the XADC Address register at Base plus 0xFBH. Next, this
register at Base plus 0xF9H is read. Data bits 15 to 6 of this register hold the

“ADCcode” temperature, Vccint, or Vccaux value. Data bits 5 to 0 are not

used. Valid addresses are given in column one of the table below.

Reading or writing this register is possible via 16-bit data transfers.

The 10-bits digitized and output from the ADC can be converted to
temperature by using the following equation.

15

.

273

1024

975

.

503

)

(

−



=



ADCcode

C

e

Temperatur

The 10-bits digitized and output from the ADC can be converted to voltage
by using the following equation.

V

ADCcode

volts

age

SupplyVolt

3

1024

)

(



=

XADC Address Register (Read/Write) - Base + FBH

This read/write register is used to set the XADC address register with a valid
address for the XADC internal status or control registers. Valid addresses
are given in the following table. Additional addresses can be found in the
Xilinx XADC document UG480 (available from Xilinx). Writing this register is
possible via 16-bit data transfers.

The address value written to this register can also be read from this register.

System Monitor Register Map

Address

Status Register

0x00

Temperature

0x01

Vccint

0x02

Vccaux

0x20

Maximum Temperature

0x21

Maximum Vccint

0x22

Maximum Vccaux

0x24

Minimum Temperature

0x25

Minimum Vccint

0x26

Minimum Vccaux

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Summary of Contents for AVME9670A Series

Page 1: ...gent Carrier Boards USER S MANUAL ACROMAG INCORPORATED 30765 South Wixom Road Wixom MI 48393 2417 U S A Tel 248 295 0310 Email solutions acromag com Copyright 2020 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8501170A ...

Page 2: ... Information 6 1 3 2 Key Features 6 1 3 3 Key Features VME64x bus Interface 7 1 4 Signal Interface Products 8 1 5 Software Support 9 Windows 9 VxWorks 9 Linux 9 2 0 PREPARATION FOR USE 10 2 1 Unpacking and Inspecting 10 2 2 Card Cage Considerations 11 2 3 Board Configuration 11 2 4 VME64x Bus Interface Configuration 11 2 5 Address Decode Jumper Configuration 11 Table 2 1 Address Decode Jumper Sele...

Page 3: ...ard Registers 23 3 1 Identification ROM Read Only 32 Odd Byte Addresses 25 Table 3 2 Generic IP Module ID Space Identification ID ROM 26 3 2 Carrier Board Status Register Read Write Base C1H 26 3 3 Interrupt Level Register Read Write Base C3H 28 3 4 IP Error Register Read Base C5H 29 3 5 IP Memory Enable Register Read Write Base C7H 29 3 6 IP Memory Base Address Size Register Read Write 30 IP_A Ba...

Page 4: ...Y OF OPERATION 37 4 1 CARRIER BOARD OVERVIEW 37 4 2 VME64x bus Interface 37 4 3 Carrier Board Registers 38 4 4 IP Logic Interface 39 4 5 Carrier Board Clock Circuitry 39 4 6 IP Read and Write Cycle Timing 40 4 7 VME64x Bus Interrupter 41 4 8 Power Failure Monitor 42 4 9 Access LEDs and Pulse Stretcher Circuitry 42 4 10 Power Supply Filters 42 4 11 Power Supply Fuses 42 5 0 SERVICE AND REPAIR 43 5 ...

Page 5: ...able 6 4 1 AVME9670A 46 6 5 INDUSTRIAL I O PACK COMPLIANCE 46 6 6 VME64x bus COMPLIANCE 47 APPENDIX 48 CABLE MODEL 5028 187 SCSI 2 to Flat Ribbon Shielded 48 Termination Panel Model 5025 552 48 VME64x TRANSITION MODULE MODEL TRANS 200 49 DRAWINGS 50 4501 755 AVME9670A JUMPER IP LOCATIONS 50 4501 756 MECHANICAL ASSEMBLY DRAWING 51 4501 757 AVME9670A BLOCK DIAGRAM 52 4501 758 CABLE SCSI 2 to Flat Ri...

Page 6: ...emark Trade Name and Copyright Information 2017 by Acromag Incorporated All rights reserved Acromag and Xembedded are registered trademarks of Acromag Incorporated All other trademarks registered trademarks trade names and service marks are the property of their respective owners 1 2 2 Class A Product Warning This is a Class A product In a domestic environment this product may cause radio interfer...

Page 7: ...ports accesses to IP input output memory identification data and interrupt spaces Full IP Register Access Makes maximum use of logically organized programmable registers on the carrier boards to provide for easy configuration and control of IP modules The only hardware jumper settings required on the carrier boards set the base address of the card in the VME64x bus short I O space LED Indicators S...

Page 8: ... the IP modules per the IP specification Individually Filtered Power Filtered 5V 12V and 12V DC power is provided to the IP modules via passive filters present on each supply line serving each IP This provides optimum filtering and isolation between the IP modules and the carrier board and allows analog signals to be accurately measured or reproduced on IP modules without signal degradation from t...

Page 9: ...to all industry standard 8 MHz IP modules Acromag provides the following interface products all connections to field signals are made through the carrier board and transition module which passes them to the individual IP modules Cables Model 5028 187 SCSI 2 to Flat Ribbon Cable Shielded A round 50 conductor shielded cable with a male SCSI 2 connector at one end and a flat female ribbon connector a...

Page 10: ...ly to facilitate the development of Windows applications interfacing with Industry Pack modules This software model IPSW API WIN consists of low level drivers and Dynamic Link Libraries DLLs that are compatible with a number of programming environments The DLL functions provide a high level interface to boards eliminating the need to perform low level reads writes of registers and the writing of i...

Page 11: ...electromagnetic magnetic or radioactive fields unless the device is contained within its original manufacturer s packaging Be aware that failure to comply with these guidelines will void the Acromag Limited Warranty 2 1 Unpacking and Inspecting Upon receipt of this product inspect the shipping carton for evidence of mishandling during transit If the shipping carton is badly damaged or water staine...

Page 12: ...sible configuration settings will be discussed in the following Sections The jumper locations and IP module positions are shown in Drawing 4501 755 Power should be removed from the board when installing IP modules cables termination panels and field wiring Refer to Mechanical Assembly Drawing 4501 756 and your IP module documentation for specific configuration and assembly instructions 2 4 VME64x ...

Page 13: ...T OUT IN 0800 OUT OUT OUT OUT IN OUT 0C00 OUT OUT OUT OUT IN IN 1000 OUT OUT OUT IN OUT OUT EC00 IN IN IN OUT IN IN F000 IN IN IN IN OUT OUT F400 IN IN IN IN OUT IN F800 IN IN IN IN IN OUT FC00 IN IN IN IN IN IN Consult your host CPU manual for detailed information about addressing the VME64x bus short I O A16 16 bit space In many cases CPU s utilizing 24 bit addressing will start the 16 bit addre...

Page 14: ...ee jumper IP location drawing 4501 756 for physical locations of the IP modules SCSI 2 Round cable assemblies and Acromag termination panels or user defined terminations can be quickly mated to the transition module connectors Pin assignments are defined by the IP I O Mapping to VME64x Standard ANSI VITA 4 1 1996 Connectors A through D are 50 pin SCSI 2 right angle female connectors AMP Connectors...

Page 15: ...3 and P14 are 50 pin male plug header connectors These AMP 173280 3 connectors mate to AMP 173279 3 connectors or similar on the IP modules This provides excellent connection integrity and utilizes gold plating in the mating area Threaded metric M2 screws and spacers supplied with Acromag IP modules provide additional stability for harsh environments see Drawing 4501 756 for assembly details Pin a...

Page 16: ...signments for the VME64x bus signals at the P1 connector The P1 connector is the upper rear connector on the AVME9670A board as viewed from the front The connector consists of 32 rows of five pins labeled A B C D and Z Pin Z1 is located at the upper right hand corner of the connector if the board is viewed from the front component side Refer to the VME64x bus specification for additional informati...

Page 17: ...3 3V 25 RsvBus A06 IRQ6 A13 RsvBus 26 GND A05 IRQ5 A12 3 3V 27 RsvBus A04 IRQ4 A11 LI I 28 GND A03 IRQ3 A10 3 3V 29 RsvBus A02 IRQ2 A09 LI O 30 GND A01 IRQ1 A08 3 3V 31 RsvBus 12V 5VSTDBY 12V GND 32 GND 5V 5V 5V VPC Asterisk is used to indicate an active low signal Shaded area are pins defined under the VME64 bus specification BOLD ITALIC Logic Lines are NOT USED by the carrier board Elongated mat...

Page 18: ...13 B14 A15 Not Used A16 B15 14 GND A17 Not Used A18 B16 15 B17 A19 Not Used A20 B18 16 GND A21 Not Used A22 B19 17 B20 A23 Not Used A24 B21 18 GND A25 Not Used A26 B22 19 B23 A27 Not Used A28 B24 20 GND A29 Not Used A30 B25 21 B26 A31 Not Used A32 B27 22 GND A33 Not Used A34 B28 23 B29 A35 Not Used A36 B30 24 GND A37 Not Used A38 B31 25 B32 A39 Not Used A40 B33 26 GND A41 Not Used A42 B34 27 B35 A...

Page 19: ...pin assignments for the VME64x bus signals at the P0 connector The P0 connector is the center connector on the AVME9670A board as viewed from the front The connector consists of 6 rows of 19 pins labeled A B C D E and F Pin A1 is located at the upper right hand corner of the connector near the center of the board viewed from the front component side The I O signals for the P0 connector are mapped ...

Page 20: ...AVME9670A board uses a Field Programmable Gate Array FPGA to handle the bus interface and control logic timing Upon power up the FPGA automatically clocks in configuration vectors from a local PROM to initialize the logic circuitry for normal operation This time is measured as the first 145mS typical after the 5 Volt supply rises to 2 5 Volts at power up The VME64x bus specification requires that ...

Page 21: ...P module This provides maximum filtering and signal isolation between the IP modules and the carrier board However the boards are considered non isolated since there is electrical continuity between the VME64x bus and the IP grounds Therefore unless isolation is provided on the IP module itself the field I O connections are not isolated from the VME64x bus Care should be taken in designing install...

Page 22: ...ion of the carrier board The memory map for the AVME9670A is shown in Table 3 1A The Input Output IO and Identification ID spaces of each IP are accessible via the VME64x bus Short I O space as shown in Tables 3 1A The carrier board may optionally occupy memory in the VME64x bus standard A24 address space if needed for IP modules containing Memory space IP memory will only be mapped into the stand...

Page 23: ...7F 0180 01BE Not Used IP B ID Space Low Byte 0181 01BF 01C0 01FE Not Used Not Used 01C1 01FF 0200 027E IP C I O Space High Byte IP C I O Space Low Byte 0201 027F 0280 02BE Not Used IP C ID Space Low Byte 0281 02BF 02C0 02FE Not Used Not Used 02C1 02FF 0300 037E IP D I O Space High Byte IP D I O Space Low Byte 0301 037F 0380 03BE Not Used IP D ID Space Low Byte 0381 03BF 03C0 03FE Not Used Not Used...

Page 24: ...d Carrier Board Status Register 00C1 00C2 Not Used Interrupt Level Register 00C3 00C4 Not Used IP Error Register 00C5 00C6 Not Used IP Memory Enable Register 00C7 00C8 00CE Not Used Not Used 00C9 00CF 00D0 Not Used IP_A Memory Base Address Size Register 00D1 00D2 Not Used IP_B Memory Base Address Size Register 00D3 00D4 Not Used IP_C Memory Base Address Size Register 00D5 00D6 Not Used IP_D Memory...

Page 25: ...ble Register 00E1 00E2 Not Used IP Interrupt Pending Register 00E3 00E4 Not Used IP Interrupt Clear Register 00E5 00E6 00EE Not Used Not Used 00E7 00EF 00F0 Firmware Revision 00F1 00F2 Flash Data Reserved 00F3 00F4 Flash Chip Select Reserved 00F5 00F6 Not Used 00F7 00F8 XADC Status Control Register 00F9 00FA XADC Address Register 00FB 00FB 00FE Not Used Not Used 00FC 00FF ...

Page 26: ...ID ROM Format I Both fixed and variable information may be present within the ID ROM Fixed information includes the IPAC identifier model number and manufacturer s identification codes Variable information may include unique information required for the module The identification Section for each IP module is located in the carrier board memory map per Table 3 1A ID bytes are addressed using only t...

Page 27: ...1 07 C 43 09 A3 Acromag ID Code 0B mm IP Model Code1 0D 00 Not Used Revision 0F 00 Reserved 11 00 Not Used Driver ID Low Byte 13 00 Not Used Driver ID High Byte 15 nn Total Number of ID PROM Bytes 17 cc CRC 19 to 2 nn 1 xx IP Specific Space 2 nn 1 to 3F yy Not Used Notes Table 3 2 1 The IP model number is represented by a two digit code within the ID ROM e g the IP405 model is represented by 01 He...

Page 28: ...t is set to 0 automatic acknowledgement is enabled The carrier will acknowledge the access even if the IP module does not or if there is no IP module present Bit 5 of this register will be set to indicate that the last IP module access has timed out Bit 5 Timed Out Access This bit when set to 1 indicates that the last IP module has timed out The IP did not acknowledge the access This bit will be 0...

Page 29: ...terrupt level Note that the Global Interrupt Enable bit in the Carrier Board Status Register must be set for interrupts to be enabled from the carrier board Also the specific IP interrupt request must be enabled via its corresponding bit in the Interrupt Enable Register described subsequently MSB D7 D6 D5 D4 D3 D2 D1 LSB D0 Not Used Not Used Not Used Not Used Not Used IL2 IL1 IL0 Where Bits 7 6 5 ...

Page 30: ... Where Bits 7 6 5 4 3 2 1 Not used equal 0 if read Bit 0 IP Error Read This bit will be a 1 when any IP module asserts its Error signal This bit will be 0 when there is no error Reset Condition Bit will be 0 no error unless driven by IP 3 5 IP Memory Enable Register Read Write Base C7H The IP Memory Enable Register allows the user to program which IP modules will be accessible in the standard A24 ...

Page 31: ... the memory space for IP A A zero disables memory space accesses Reset Condition Set to 0 memory space accesses disabled for IP A 3 6 IP Memory Base Address Size Register Read Write IP_A Base D1H IP_B Base D3H IP_C Base D5H IP_D Base D7H The IP Memory Base Address Size Registers are user programmable to define the starting address of standard A24 memory space and the size of that memory space corr...

Page 32: ...ally enable disable IP interrupts Each IP A through D may have up to two requests Note that the Global Interrupt Enable bit in the Carrier Board Status Register must be set for interrupts to be enabled from the carrier board The user must also configure the VME64x bus interrupt level using the Interrupt Level Register MSB D7 D6 D5 D4 D3 D2 D1 LSB D0 IP D Int1 Ena IP D Int0 Ena IP C Int1 Ena IP C I...

Page 33: ...flect the IP modules pending interrupt status even if the IP interrupt enable bit is set to 0 Reset Condition Set to 0 3 9 IP Interrupt Clear Register Write Base E5H The IP Interrupt Clear Register is used to individually clear the IP interrupt Pending bits set in the IP Interrupt Pending register MSB D7 D6 D5 D4 D3 D2 D1 LSB D0 IP D Int1 Clear IP D Int0 Clear IP C Int1 Clear IP C Int0 Clear IP B ...

Page 34: ...ble via 16 bit data transfers The 10 bits digitized and output from the ADC can be converted to temperature by using the following equation 15 273 1024 975 503 ADCcode C e Temperatur The 10 bits digitized and output from the ADC can be converted to voltage by using the following equation V ADCcode volts age SupplyVolt 3 1024 XADC Address Register Read Write Base FBH This read write register is use...

Page 35: ...result in constant LED illumination The LED s indicate I O memory interrupt acknowledge and ID space accesses Note that the LED s will not illuminate during accesses of carrier board registers or accesses to IP modules which are not physically present or to unsupported memory space Additional information about the error status of the IP modules can be obtained by reading the IP Error Register 3 12...

Page 36: ...P Interrupt Enable Register bits corresponding to the IP interrupt request to be enabled 6 Enable interrupts from the carrier board by writing a 1 to bit 3 global interrupt enable bit in the Carrier Board Status Register 3 14 Sequence of Events for an Interrupt 1 The IP asserts an interrupt request to the carrier board asserts IntReq0 or IntReq1 2 The AVME9670A carrier board acts as an interrupter...

Page 37: ...equired to remove the interrupt request at its source C Clear the interrupting IP by writing a 1 to the appropriate bit in the IP Interrupt Clear Register D Enable the interrupting IP by writing a 1 to the appropriate bit in the IP Interrupt Enable Register 8 If the IP interrupt stimulus has been removed and no other IP modules have interrupts pending the interrupt cycle is completed i e the carri...

Page 38: ...he transition module TRANS 200 to the Termination Panel At the Termination Panel field I O signals are connected to a 50 position terminal block via screw clamps The AVME9670A contains four IP modules and thus 200 I O connections are provided via the transition module through four SCSI 2 connectors marked A B C and D The VME64x bus and IP module logic commons have a direct electrical connection i ...

Page 39: ...r allowing communication with the carrier board s registers or IP modules 4 3 Carrier Board Registers The carrier board registers presented in section 3 are implemented in the logic of the carrier board s FPGA An outline of the functions provided by the carrier board registers includes Software reset can be issued to reset the FPGA Logic and all IP modules present on the carrier board via the Stat...

Page 40: ...ed by the carrier board s FPGA The VME64x bus to IP logic interface link allows a VME64x bus master to Access up to 32 ID Space bytes for IP module identification ID ROM Data Format I via D08 O data transfers using VME64x bus A16 short address space Access up to 128 I O Space bytes of IP data via D16 D08 EO data transfers using VME64x bus A16 short address space Access up to 8Mbytes of IP data map...

Page 41: ...are then synchronized to the IP 8MHz clock as required by the IP module specification Thus typically one 8MHz clock cycle later an IP select line goes active IOSEL IDSEL MEMSEL or INTSEL and is held active for one clock cycle With no IP wait states an active IP Acknowledge ACK signal is driven by the IP on the next rising edge of the 8MHz clock The carrier board samples ACK one clock cycle later a...

Page 42: ...tails The carrier board releases the interrupt to the VME64x bus by asserting the interrupt request level as pre programmed in the carrier s Interrupt Level Register The carrier board s interrupt logic then monitors the VME64x bus Interrupt Acknowledge Input IACKIN signal An active IACKIN signal detected by the carrier board is either passed to Interrupt Acknowledge Output IACKOUT or consumed by t...

Page 43: ...edged data transfer activates the pulse stretcher circuit The pulse stretcher s circuit is programmed to illuminate the LED for a duration of 0 125 seconds typical 4 10 Power Supply Filters Power line filters are dedicated to each IP module for filtering of the 5 12 and 12 volt supplies The power line filters are a T type filter circuit comprising ferrite bead inductors and a feed thru capacitor T...

Page 44: ...edure CAUTION POWER MUST BE TURNED OFF BEFORE SERVICING BOARDS Before beginning repair be sure that all of the procedures in Section 2 Preparation For Use have been followed Also refer to the documentation of your carrier board to verify that it is correctly configured Replacement of the carrier and or IP with one that is known to work correctly is a good technique to isolate a faulty board 5 3 Wh...

Page 45: ...lent 6 2 Power Requirements Board power requirements are a function of the installed IP modules This specification lists currents for the carrier boards only The carrier boards individually filter and provide 5V 12V and 12V power to each IP from the VME64x bus Note that the VME64x bus standard does not support 15V and 15V supplies but the carrier boards are designed to handle these if needed for u...

Page 46: ...oard only add the IP module currents for the total current required from each supply Summarized below are the expected current draws for each of the specified power supply voltages Power Supply Voltage Current Draw 5 0 VDC 5 0 290 A Typical 0 330 A maximum 12 VDC 5 Not Used 12 VDC 5 Not Used Non Isolated VMEbus and IP module logic commons have a direct electrical connection As such unless the IP m...

Page 47: ...not cause harmful interference and 2 this device must accept any interference received including interference that may cause undesired operation 6 4 Reliability Prediction Table 6 4 1 AVME9670A MTBF Mean Time Between Failure MTBF in hours using MIL HDBK 217F FN2 Per MIL HDBK 217 Ground Benign Controlled GBGC Temperature MTBF Hours MTBF Years Failure Rate FIT1 25 C 922 858 105 3 1 083 6 40 C 627 38...

Page 48: ...ress is hardware jumper selectable Occupies 1K byte Responds to both address modifiers 29H 2DH in the VMEbus short I O space for carrier board registers and IP I O and ID PROM spaces Base address is hardware jumper selectable Occupies 1K byte Responds to both address modifiers 29H 2DH in the VME64x bus short I O space for carrier board registers and IP I O and ID spaces Standard Address Space Resp...

Page 49: ...nd IDC 50 pin female connector with strain relief Keying The SCSI 2 connector has a D Shell and the IDC connector has a polarizing key to prevent improper installation Schematic and Physical Attributes See Drawing 4501 758 Shipping Weight 1 0 pound 0 5Kg packed Termination Panel Model 5025 552 Type Termination Panel For AVME967xA Boards Application To connect field I O signals to the Industrial I ...

Page 50: ...Standard 1101 11 1998 for 80 mm depth Connects to Acromag termination panel 5025 552 from the rear of the card cage and to AVME9670A AVME9675A boards within card cage via connectors RP0 and RP2 Schematic and Physical Attributes See Drawing 4501 760 Field Wiring Four SCSI 2 50 pin female connectors AMP 787082 5 or equivalent employing latch blocks and 30 micron gold in the mating area per MIL G 452...

Page 51: ...INDUSTRIAL I O PACK SERIES AVME9675A VME64x bus 6U CARRIER BOARD Acromag Inc Tel 248 295 0310 50 http www acromag com 50 https www acromag com Drawings 4501 755 AVME9670A JUMPER IP LOCATIONS 4501 755A ...

Page 52: ...INDUSTRIAL I O PACK SERIES AVME9675A VMEx64 bus 6U CARRIER BOARD Acromag Inc Tel 248 295 0310 51 http www acromag com 51 https ww acromag com 4501 756 MECHANICAL ASSEMBLY DRAWING 4501 756A ...

Page 53: ... SERIES AVME9675A VME64x bus 6U CARRIER BOARD Acromag Inc Tel 248 295 0310 52 http www acromag com 52 https www acromag com 4501 757 AVME9670A BLOCK DIAGRAM 4501 758 CABLE SCSI 2 to Flat Ribbon Shielded 5028 187 4501 757A ...

Page 54: ...INDUSTRIAL I O PACK SERIES AVME9675A VMEx64 bus 6U CARRIER BOARD Acromag Inc Tel 248 295 0310 53 http www acromag com 53 https ww acromag com ...

Page 55: ...INDUSTRIAL I O PACK SERIES AVME9675A VME64x bus 6U CARRIER BOARD Acromag Inc Tel 248 295 0310 54 http www acromag com 54 https www acromag com 4501 464 TERMINATION PANEL 5025 552 4 5 0 1 4 6 4 A ...

Page 56: ...INDUSTRIAL I O PACK SERIES AVME9675A VMEx64 bus 6U CARRIER BOARD Acromag Inc Tel 248 295 0310 55 http www acromag com 55 https ww acromag com 4501 760 VME64x Transition Mod TRANS 200 4501 760B ...

Page 57: ...ic blocks and RAM blocks Process to Sanitize Power Down Type SRAM SDRAM etc Size User Modifiable Yes No Function Process to Sanitize Non Volatile Memory Does this product contain Non Volatile memory i e Memory of whose contents is retained when power is removed Yes No Type EEPROM Flash etc Flash Size 128 Meg x 1bit User Modifiable Yes No Function Data storage for FPGA Process to Sanitize Erase usi...

Page 58: ...OARD Acromag Inc Tel 248 295 0310 57 http www acromag com 57 https ww acromag com Revision History The revision history for this document is summarized in the table below Release Date Version EGR DOC Description of Revision 25 SEP 2020 A GJB AMM Initial Release ...

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