Acromag ACPS3310, User Manual, Page: 17 / 25

AcroPack Series ACPS3310 CompactPCI-Serial Carrier Board
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JTAG Programming/Debug Connector
A JTAG programming/debug connector is provided for developing applications
that use Acromag’s FPGA AcroPack modules. See reference designator P9 in
Figure 1. This is a standard 14-pin Xilinx programming header for connecting a
Xilinx Platform USB II programming device (or equivalent). The pin assignment
for P9 is shown in Table 5. A bypass circuit is included that will detect a vacant
AcroPack site and close a switch to bypass the TDI and TDO signals. A CPLD on
the carrier is included in the JTAG chain. The Xilinx Vivado tools can detect the
presence of the CPLD in the JTAG chain and skip it when accessing the FPGAs
on the AcroPack modules.
Table 5 JTAG Programming/Debug Connector Pin Assignment
Signal Pin Pin Signal
N.C.
1
1 2 _+3.3V
GND 3 4 TMS
GND 5 6 TCK
GND 7 8 TDO
GND 9 10 TDI
GND 11 12 N.C.
1
N.C.
1
13 14 N.C.
1
Notes:
1. N.C. – not connected