Chapter 2 4S648/4S648N BIOS Setup
2-40
Advanced Chipset Features
This section allows you to configure the system based
features of the installed chipset. This chipset manages bus
speeds and access to system memory resources, such as
DRAM and external cache. It also coordinates communica-
tions of the PCI bus. It must be stated that these items should
never be altered. The default settings are set up to provide
the best operating conditions for your system. The time you
might need to make any changes would be if you discover
that data is lost while using your system.
2.5 Advanced Chipset Features
DRAM Clock/Timing Control
Press Enter
DRAM Timing Control
By SPD
x DRAM CAS Latency
2.5T
x RAS Active Time
6T
x RAS Precharge Time
3T
x RAS to CAS Delay (tRCD)
3T
DRAM Addr/Cmd Rate
AGP & P2P Bridge Control
Press Enter
AGP Aperture Size
64MB
Graphic Window WR Combin
Disabled
Prefetch Caching
Disabled
System BIOS Cacheable
Enabled
Video RAM Cacheable
Enabled
Memory Hole at 15M-16M
Disabled
Phoenix - AwardBIOS CMOS Setup Utility
←→↑↓
: Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Fail-Safe Defaults F7:Optimized Defaults
Item Help
