Acorn Computers Limited Winchester disk 110, Service Manual, Page: 19 / 43

5.2 The 1MHz expansion bus
The following is a description of the 1MHz expansion bus signals used by the
Winchester Disc Host Adapter, and their function as applied to the Winchester
Disc system. For a full description of the 1MHz expansion bus see "BBC
Microcomputer Application Note Number 1 - 1MHz Bus", part number 0407,000,
published by Acorn Computers Limited.
5.2.1 Control, address and data lines
1MHzE (system 1MHz, pin 4) is a continuously running 1MHz timing signal.
During access to the 1MHz bus, the processor clock (normally 2MHz) is
stretched so that the trailing edges of 1MHzE and the processor clock are
synchronised.
R/NW (read/not-write, pin 2) is the system read/write line.
NIRQ (not-IRQ, pin 8) is the interrupt request line which is open collector
and asserted by a device pulling it low. IRQ is level triggered active-low.
NRST (not-reset, pin 14) is output only active-low system reset line. It is
active on power-up and when the BREAK key is pressed.
NPGFC (not-page &FC, pin 10) is a signal decoded from the top 8 system address
lines (A8 to A15). NPGFC is an active-low signal which is low when the address
high byte is &FC, ie when the full address is &FC00 to &FCFF. Four locations
in this range are used by the Winchester system: &FC40 to &FC43 inclusive, see
7.2.
A0 to A7 (address low, pins 27 to 34) are the bottom 8 system address lines.
D0 to D7 (system data bus) are the bi-directional data lines. Direction
determined by R/NW. The data lines are buffered, and the buffer enabled only
when NPGFC is active.
Pins 1 3 5 7 9 11 13 15 17 and 26 are 0V. 5.2.
2 Connector pinout
TOP Pin No BOTTOM
0V 1 2 R/NW
0V 3 4 1MHzE
0V 5 6 For other applications
0V 7 8 NIRQ
0V 9 10 NPGFC
0V 11 12 For other applications
0V 13 14 NRST
0V 15 16 For other applications
0V 17 18 D0
D1 19 20 D2
D3 21 22 D4
D5 23 24 D6
D7 25 26 0V
A0 27 28 Al
A2 29 30 A3
A4 31 32 A5
A6 33 34 A7
14