Manual 104-QUAD-8
15
Writing to the RLD (Reset and Load Signal Decoders):
Bit 0:
1 to reset BP.
Bits 1 & 2:
Set bit 1 high to reset CNTR, set bit 2 high to reset BT, CT, CPT, S flags.
Set both bits high to reset E flag.
Bits 3 & 4:
Set bit 3 high to transfer Preset Register to Counter.
Set bit 4 high to transfer CNTR to Output Latch.
Set both high to transfer Preset Register LSB to the PSC (FCK Prescaler).
Bits 5 & 6:
Set both bits to 0.
Bit 7:
Set high to program both counters simultaneously.
Writing to the CMR (Counter Mode Register):
Bit 0:
Set low to use Binary count, and set high to use BCD count.
Bits 1 & 2:
Set both low to use Normal count.
Set bit 1 high to use Range Limit.
Set bit 2 high to use Non-Recycle count.
Set both bits high to use Modulo-N count.
Bits 3 & 4:
Set both bits low to use non-quadrature mode.
Set bit 3 high to use Quadrature times 1.
Set bit 4 high to use Quadrature times 2.
Set both bits high to use Quadrature times 4.
Bits 5 & 6:
Set bit 5 high and bit 6 low.
Bit 7:
Set high to program both counters simultaneously.
Writing to the IOR (Input / Output Control Register):
Bit 0:
Set high to enable A and B inputs.
Bit 1:
Set low to preset count when Index occurs.
Set high to continuously count.
Bit 2:
Set low.
Bits 3 & 4:
Set both bits low to use FLG1 as /Carry (active low).
Set bit 3 high to use FLG1 as /Compare (active low).
Set bit 4 high to use FLG1 as /Carry/Borrow (active low).
Set both bits high to use FLG1 as Index (active high).
Bits 5 & 6:
Set bit 5 low and bit 6 high.
Bit 7:
Set high to program both counters simultaneously.
Note that when Interrupts are enabled on the card they occur whenever FLG1 is active.
