Digital I/O
Please refer to the data sheets and 8255-5 specification in the ‘Chip Docs’ directory on the CD.
The board uses two 8255-5 PPIs to provide a total of 48 bits input/output. The board is designed to use
each of these PPIs in Mode 0 wherein for each group:
a.
There are two 8-bit ports (A and B) and two 4-bit ports (C Hi and C Lo).
b.
Any port can be configured as an input or an output.
c.
Outputs are latched.
d.
Inputs are not latched.
Each PPI contains a Control Register. This write-only, 8-bit register is used to set the mode and
direction of the ports. At Power-Up or Reset, all I/O lines are set as inputs. Each PPI should be
configured during initialization by writing to the Control Registers even if the ports are only going to be
used as inputs. Output buffers are automatically set by hardware according to the Control Register
states. Note that Control Registers are located at base a3 and base a7. Bit
assignments in each of these Control Registers are as follows:
Bit
Assignment
Code
D0 Bit
Port C Lo (C0-C3)
1=Input, 0=Output
D1
Port B
1=Input, 0=Output
D2
Mode Select
1=Mode 1, 0=Mode 0
D3
Port C Hi (C4-C7)
1=Input, 0=Output
D4
Port A
1=Input, 0=Output
D5, D6
Mode Select
00=Mode 0, 01=Mode 1, 1X=Mode
2
D7
Mode Set Flag
1=Active
Table 5-2:
Control Register Bit Assignment
Note
Mode 1 and Mode 2 cannot be used by the board without modification (Consult the factory.). Thus, bits D2, D5,
and D6 should always be set to "0" and, when the TST/BEN jumper is in the BEN position, Bit D7 to "1". The
hardware will reject any command in which bits D2, D5, and D6 aren’t zero.
Note
In Mode 0, do not use the control register byte for the individual bit control feature. The hardware uses the I/O
bits to control buffer direction on this board. The control register should only be used for setting up input and
output of the ports and enabling the buffer.
The board is initialized in the receive mode by the computer reset command.
a.
When bit D7 of the Control Register is set high, direction of the three ports of the associated PPI chip
as well as the mode can be set. For example, a write to Base A3 with data bit D7 high
programs port direction at Group 0 ports A, B, and C. If, for example, hex 80 is sent to Base Address
+3, the Group 0 PPI will be configured in mode 0 with Ports A, B, and C as outputs.
Manual 104-DIO-48E, 24E
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