Abov MC96F6432 Series, User Manual

Page: 247 / 327

MC96F6432
June 22, 2018 Ver. 2.9 247
11.13.14 USI1 I2C Mode
The USI1 can be set to operate in industrial standard serial communication protocols mode. The I2C mode uses
2 bus lines serial data line (SDA1) and serial clock line (SCL1) to exchange data. Because both SDA1 and SCL1
lines are open-drain output, each line needs pull-up resistor. The features are as shown below.
- Compatible with I2C bus standard
- Multi-master operation
- Up to 400kHz data transfer read speed
- 7 bit address
- Both master and slave operation
- Bus busy detection
11.13.15 USI1 I2C Bit Transfer
The data on the SDA1 line must be stable during HIGH period of the clock, SCL1. The HIGH or LOW state of
the data line can only change when the clock signal on the SCL1 line is LOW. The exceptions are START(S),
repeated START(Sr) and STOP(P) condition where data line changes when clock line is high.
Figure 11.88 Bit Transfer on the I2C-Bus (USI1)
SCL1
SDA1
Data line Stable:
Data valid
except S, Sr, P
Change of Data
allowed