Abit SL6, User Manual

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3-22 Chapter3
SL6
The first chipset settings deal with CPU access to DRAM. The default timings have been
carefully chosen and should only be altered if data is being lost. Such a scenario might well
occur if your system has mixed speed DRAM chips installed. In such a case, greater delays
may be required to preserve the integrity of the data held in the slower memory chips.
SDRAM CAS Latency Time:
Two options are available: 2 and 3. The default setting is 3 . You can select SDRAM CAS
(Column Address Strobe) latency time according your SDRAM specification.
SDRAM Cycle Time Tras/Trc:
Two options are available: 5/7 and 6/8. The default setting is 6/8 . This item controls the
number of SDRAM clocks (SCLKs) used per access cycle.
SDRAM RAS-to-CAS Delay
Two options are available: 2 and 3. The default setting is 3 . This item lets you insert a timing
delay between the CAS and RAS strobe signals, used when DRAM is written to, read from,
or refreshed.
Fast (2) gives faster performance; and Slow(3) gives more stable performance.
This item applies only when synchronous DRAM is installed in the system.
SDRAM RAS Precharge Time:
Two options are available: 2 and 3. The default setting is 3 . This option lets you insert a
timing delay between the CAS and RAS strobe signals, used when DRAM is written to, read
from, or refreshed.
Fast (2) gives faster performance; and Slow (3) gives more stable
performance. This item applies only when synchronous DRAM is installed in the system.
System BIOS Cacheable:
You can select Enabled or Disabled. The default setting is Enabled . When you select
Enabled allows caching of the system BIOS ROM at F0000h-FFFFFh, resulting in better
system performance. However, if any program writes to this memory area, a system error
may result.
Video BIOS Cacheable:
You can select Enabled or Disabled. The default setting is Enabled . Enabled allows