Hardware Setup
2-17
(14). POST Code Display [U32]
This is an LED device to display the “
POST
” Code, the acronym of
P
ower
O
n
S
elf
T
est. The computer
will execute the POST action whenever you power on the computer. The POST process is controlled by
the BIOS. It is used to detect the status of the computer’s main components and peripherals. Each POST
Code corresponds to different checkpoints that are also defined by the BIOS in advance. For example,
“memory presence test” is an important checkpoint and its POST Code is “C1”. When the BIOS execute
any POST item, it will write the corresponding POST Code into the address 80h. If the POST passes, the
BIOS will process the next POST item and write the next POST Code into the address 80h. If the POST
fails, we can check the POST Code in address 80h to find out where the problem lies.
The following table shows the POST Code in detail:
POST
Code
Description
CF
Test CMOS R/W functionality
C0
Early chipset initialization:
-Disable shadow RAM
-Disable L2 cache (socket 7 or below)
-Program basic chipset registers
C1
Detect memory
-Auto-detection of DRAM size, type and ECC
-Auto-detection of L2 cache (socket 7 or below)
C3
Expand compressed BIOS code to DRAM
C5
Call chipset hook to copy BIOS back to E000 & F000 shadow RAM
01
Expand the Xgroup codes locating in physical address 1000:0
03
Initial Superio_Early_Init switch
05
1. Blank out screen
2. Clear CMOS error flag
07
1. Clear 8042 interface
2. Initialize 8042 self-test
08
1. Test special keyboard controller for Winbond 977 series Super I/O chips
2. Enable keyboard interface
User’s Manual
Summary of Contents for SI7
Page 1: ...SI7 Series SI7 SI7 G Socket 478 System Board User s Manual 4200 0346 02 Rev 1 00 ...
Page 19: ...Introduction 1 3 1 2 Layout Diagram User s Manual ...
Page 20: ...1 4 Chapter 1 1 4 Chapter 1 SI7 Series SI7 Series ...
Page 66: ...A 2 Appendix A A 2 Appendix A SI7 Series SI7 Series ...
Page 68: ...B 2 Appendix B B 2 Appendix B SI7 Series SI7 Series ...
Page 76: ...E 2 Appendix E SI7 Series ...
