bdi
CW
BDM interface for CodeWarrior™ Debugger, BDI2000 (MPC5xx/8xx)
User Manual
5
© Copyright 1992-2001 by ABATRON AG
V 1.02
BDI MAIN / TARGET A Connector Signals:
Mention of sources used: MPC860ADS User’s Manual, Revision A
Enhanced Debug Mode Detection:
For MPC8xx and MPC555 targets, debug mode (Freeze) detection also works when the BDM con-
nector pins VFLS0 and VFLS1 are not connected to the target. If not connected to VFLSx, this BDM
connector pins should be left open or tied to Vcc. The BDI uses the following algorithm to check if the
target is in debug mode (freezed):
BOOL PPC_TargetFreezed(void) {
if ((VFLS0 != 1) | (VFLS0 != 1)) return FALSE;
read debug port status;
if (status == freezed) return TRUE;
else return FALSE;
Pin
Name
Describtion
1
VFLS0
These pin and pin 6 (VFLS1) indicate to the debug port controller whether or not the MPC
is in debug mode. When both VFLS0 and VFLS1 are at "1", the MPC is in debug mode.
2
SRESET
This is the Soft-Reset bidirectional signal of the MPC8xx. On the MPC5xx it is an output.
The debug port configuration is sampled and determined on the rising-edge of SRESET
(for both processor families). On the MPC8xx it is a bidirectional signal which may be driven
externally to generate soft reset sequence. This signal is in fact redundant regarding the
MPC8xx debug port controller since there is a soft-reset signal integrated within the debug
port protocol. However, the local debug port controller uses this signal for compatibility with
MPC5xx existing boards and s/w.
3+5
GND
System Ground
4
DSCK
Debug-port Serial Clock
During asynchronous clock mode, the serial data is clocked into the MPC according to the
DSCK clock. The DSCK serves also a role during soft-reset configuration.
6
VFLS1
These pin and pin 1 (VFLS0) indicate to the debug port controller whether or not the MPC
is in debug mode. When both VFLS0 and VFLS1 are at "1", the MPC is in debug mode.
7
HRESET
This is the Hard-Reset bidirectional signal of the MPC. When this signal is asserted (low)
the MPC enters hard reset sequence which include hard reset configuration. This signal is
made redundant with the MPC8xx debug port controller since there is a hard-reset com-
mand integrated within the debug port protocol.
8
DSDI
Debug-port Serial Data In
Via the DSDI signal, the debug port controller sends its data to the MPC. The DSDI serves
also a role during soft-reset configuration.
9
Vcc Target
1.8 – 5.0V:
This is the target reference voltage. It indicates that the target has power and it is also used
to create the logic-level reference for the input comparators. It also controls the output logic
levels to the target. It is normally fed from Vdd I/O on the target board.
3.0 – 5.0V with Rev. A/B :
This input to the BDI2000 is used to detect if the target is powered up. If there is a current
limiting resistor between this pin and the target Vdd, it should be 100 Ohm or less.
10
DSDO
Debug-port Serial Data Out
DSDO is clocked out by the MPC according to the debug port clock, in parallel with the
DSDI being clocked in. The DSDO serves also as "READY" signal for the debug port con-
troller to indicate that the debug port is ready to receive controller’s command (or data).