abaco systems V7768, Hardware Reference Manual

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52 V7768/V7769* Intel® Core™ Duo Processor VME Single Board Computer Publication No: 500-9300007768-000 Rev. H.0
When this field is read, the current count value is latched and returned. There are
two modes that determine how the count is latched depending on the setting of
the “Read Latch Select” bit in the Control Status Register (TCSR2). See the TCSR2
register description for more information on these two modes.
3.3.6 Timer 1 & 2 Current Count Register (TMRCCR12)
The current count of timers 1 & 2 may be read via the Timer 1 & 2 Current Count
Register (TMRCCR12), located at offset 0x20 from the address in BAR2. The
mapping of bits in this register is shown in
Table 3-8
.
Table 3-8 TMRCCR12 Bit Mapping
Field Bits Read or Write
Timer 2 Count TMRCCR12[31..16] Read Only
Timer 1 Count TMRCCR12[15..0] Read Only
When either field is read, the current count value is latched and returned. There
are two modes that determine how the count is latched depending on the setting
of the “Read Latch Select” bit in the Control Status Register (TCSR2). See the
TCSR2 register description for more information on these two modes.
3.3.7 Timer 3 Current Count Register (TMRCCR3)
The current count of Timer 3 may be read via the Timer 3 Current Count Register
(TMRCCR3), located at offset 0x24 from the address in BAR2. The mapping of
bits in this register is shown in
Table 3-9
.
Table 3-9 TMRCCR3 Bit Mapping
Field Bits Read or Write
Timer 3 Count TMRCCR3[31..0] Read Only
When this field is read, the current count value is latched and returned. There are
two modes that determine how the count is latched depending on the setting of
the “Read Latch Select” bit in the Control Status Register (TCSR2). See the TCSR2
register description for more information on these two modes.
3.3.8 Timer 4 Current Count Register (TMRCCR4)
The current count of Timer 4 may be read via the Timer 4 Current Count Register
(TMRCCR4), located at offset 0x28 from the address in BAR2. The mapping of
bits in this register is shown in
Table 3-10
.
Table 3-10 TMRCCR4 Bit Mapping
Field Bits Read or Write
Timer 4 Count TMRCCR4[31..0] Read Only