abaco systems SBC347A-11330001, Hardware Reference Manual

Page: 71 / 111

Publication No. 500-9300527837-000 Rev. A.0 FPGA Registers 71
6.36 VPX GDISCRETE1 Active Low/High Register (0x68D)
This sets the interrupt detection sensitivity of the GDISCRETE1 pin (active high/
low or rising/falling edge depending on sensitivity mode):
6.37 VPX GDISCRETE1 Both Edges Register (0x68E)
When enabled, both-edge mode causes interrupts to be generated on both rising
and falling edges. The GDISCRETE1 bit must be in edge mode for both-edge
mode to work:
6.38 VPX GDISCRETE1 Interrupt Status Register (0x68F)
Write a ‘1’ to bit 7 to clear the interrupt.
6.39 VPX GDISCRETE1 Availability Register (0x690)
Bits Read/Write Description Default
7 Read/Write GDISCRETE1:
1 = Active high/rising edge
0 = Active low/falling edge
Depending on whether the bit is in level or edge mode
0
6 to 0 Read only Reserved 0000000
b
Bits Read/Write Description Default
7 Read/Write GDISCRETE1:
1 = Both-edge mode enabled
0 = Both-edge mode disabled
0
6 to 0 Read only Reserved 0000000
b
Bits Read/Write Description Default
7 Read/Write GDISCRETE1:
1 = Interrupt pending
0 = No interrupt
0
6 to 0 Read only Reserved 0000000
b
Bits Read/Write Description Default
7 Read/Write GDISCRETE1:
1 = GDISCRETE1 is available
0 = GDISCRETE1 is not available
0
6 to 0 Read only Reserved 0000000
b