Publication No. 500-9300527837-000 Rev. A.0
Functional Description 39
5.5 Data Plane Fabric
In accordance with the OpenVPX Specification, the top half of the
is
allocated for the data plane connection and complies with OpenVPX module
profile MOD3-PAY-2F2T-16.2.5-3 (1000BASE-T control plane is capable of
10GBASE-T
operation)
.
The OpenVPX fabric connection is made up from an optional x2 PCIe link from
the PCH, and the bottom four lanes of the Broadwell CPU PEG port on the VPX
P1 connector. An additional four lanes of the PEG port are available on the VPX
P2 connector to make a possible x8 PEG PCIe link. Also, an optional x4 PCIe link
from the PCH is available on the P2 connector. This is shown below:
Figure 5-2 Additional PCIe Connectivity
NOTE
Optional x2 and x4 PCIe ports from the PCH are only available when I/O product option = 1.
5.5.1 PCI Express Gen3 Operation
The SBC347A PEG port lanes are compatible with PCIe Gen3 operation across the
backplane. The ability to operate at Gen3 depends on the physical parameters of
the complete channel (i.e., the backplane, the SBC347A, and the link partner), so
Gen3 operation should be verified on a system-by-system basis.
NOTE
The SBC346ARTM contains PCIe redrivers that are limited to Gen2 speed. When using the SBC347A with
the SBC346ARTM, the user must set PEG Port 0 speed to either Gen1 or Gen2 (Auto or Gen3 is not
compatible). To make these changes in the BIOS setup, go to Chipset > System Agent Configuration >
PEG Port Configuration, and set PEG Port 0 to Gen1 or Gen2.
P0
P1
P2
1
1
1
16
16
8
PEG port lanes 0 to 3
Optional x2 from PCH
Optional x4 from PCH
PEG port lanes 4 to 7
