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abaco systems RTM311, User Manual

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UM082 RTM311 User Manual 

 

r1.3 

 

UM082 

www.abaco.com 

 

 

 

page 16 of 28

 

•

 

“JTAG” via a 2X7-Way (2mm pitch) connector 

The JTAG connector has pinout compatible with Xilinx USB platform cables. See section 7.5.3.1. 

Please  note  that  care  should  be  taken  when  using  the  JTAG  cable

,  the  cable  should  be 

handled at the connector as there is no strain relief on the cable. 

•

 

“DEBUG” via a 5-Way (2.54mm pitch) connector  

 I2C interface can be used for debugging by writing to the I2C switch to connect port4. 

Pin 

VPX signal name 

1 

GPIO_DISC1, Reserved 

2 

GPIO_DISC0, Reserved 

3 

GPIO_I2C_SDA 

4 

GPIO_I2C_SCL 

5 

GND 

7.5.2.3  USB2.0 connector 

RTM311  has  a  USB3.0  hub  which  accommodates  the  use  of  both  the  USB2.0  and  USB3.0 
interfaces. The USB2.0 interface is connected to VPX backplane per table below. 

USB2.0 connector 

VPX backplane signals 

Pin1, Vcc 

Vs3 

Pin2, DATA_N 

USB2.0_DM 

Pin3, DATA_P 

USB2.0_DP 

Pin4, GND 

GND 

7.5.2.4  USB3.0 connector 

Ensure that the on-

board switch, SW5, is in “ON” position. The USB3.0 interface is connected to 

VPX backplane per table below. 

USB3.0 connector 

VPX backplane signals 

Pin1-4 

See USB2.0 

Pin5, SSRX_N 

DISP_TX-/USB3.0_TX- 

Pin6, SSRX_P 

/USB3.0_TX+ 

Pin7, GND 

GND 

Pin8, SSTX_N 

DISP_RX-/USB3.0_RX- 

Pin9, SSTX_P 

/USB3.0_RX+ 

 

Summary of Contents for RTM311

Page 1: ...co com page 1 of 28 RTM311 User Manual Abaco Systems Support Portal This document is the property of Abaco Systems Inc and may not be copied nor communicated to a third party without the written permission of Abaco Systems Inc Abaco Systems 2017 ...

Page 2: ...vk Ivk 2017 09 25 r1 1 Changed SW4 s default position to OFF Jpat Rza JDS 2017 10 20 r1 2 Added USB3 0 and DisplayPort verification and BSP details Added remark about 1000BASE T only on RJ45 s Ivk Jpat Ivk 2017 11 17 r1 3 Added Changed information on QTE M 2 SATA and DisplayPort switch position Removed ordering information and referred to PN document Jpat Ivk JDS 2018 01 10 ...

Page 3: ...ckplane keying 6 7 1 3 Front panel 6 7 1 4 Connectors location 7 7 2 ESD Protection 8 7 3 Switches 8 7 3 1 RESET button momentary switch 8 7 3 2 On board dip switches 8 7 3 3 I2C switch 9 7 4 LEDs 10 7 4 1 On board LEDs 10 7 4 2 Front panel LEDs 10 7 5 Connectors 11 7 5 1 VPX connectors 11 7 5 2 Front panel connectors 15 7 5 3 On board connectors 18 7 6 CPLD 25 7 7 Battery 25 7 8 Safety 25 7 9 EMC...

Page 4: ...i Gigabit Transceiver MSB Most Significant Bit s PCB Printed Circuit Board PCI Peripheral Component Interconnect PCIe PCI Express 3 Terms used The terms used in this document are explained as the followings On board connectors Any connectors except the VPX connectors on the RTM311 that cannot be accessed from the front panel On board switches Any switches on the RTM311 that cannot be accessed from...

Page 5: ...arries a M 2 SSD card that communicates to the VPX through SATA or PCIe The global architecture of the RTM311 is shown in Figure 1 I2C I2C I2C JTAG ctrl ctrl ctrl VPX ctrl 2x1000BASE KX Eth Phy 2x Magnet ics 2x 2x RJ45 1000BASE T 1xUSB2 0 USB3 0 Hub 1x USB2 0 1x USB3 0 1x USB2 0 1x USB3 0 JTAG JTAG CPLD I2C MDIO Display Port Driver Display Port 1x DisplayPort 1 2 1x DisplayPort 1 2 USB3 0 LEDs 1x ...

Page 6: ...2 Backplane keying Both alignment key1 and key2 are placed by default with the un keyed version 1 1469492 9 Contact Abaco Systems if specific keying is required 7 1 3 Front panel RTM311 provides various interfaces via the front panel See section 7 5 2 for more details The front panel bezel options are offered as shown below 0 8 inch IEEE 1101 10 and VITA 46 compliant 1 inch IEEE 1101 10 VITA 46 1 ...

Page 7: ...TM311 is shown in Figure 3 in section 7 1 4 3 7 1 4 2 Front panel connectors location The location of connectors is shown in the picture below Pins assignment is provided in section 7 2 Figure 2 RTM311 front panel connectors location 7 1 4 3 On board connectors locations The location of connectors is shown below Pins assignment is provided in section 7 5 3 ...

Page 8: ...ntary switch RESET button SW1 is made assessible on the front panel through a small key hole The VPX board can be reset by pressing this button 7 3 2 On board dip switches Their functionalities are explained below All switches are in ON position by default apart from SW4 which should be OFF by default Switch ON OFF SW2 NVRMO 0 NVRMO 1 SW3 M 2 SATA selected Standard SATA connector selected SW4 JTAG...

Page 9: ...ow I2C I2C I2C VPX CPLD XC2C256 7VQG100I I2C DisplayPort Driver SN65DP141 GPIO Micro HDMI PCA9548 MGT and legacy LVDS QTE 120 pins SATA Redriver DS100BR111 TCA9517 Side A Side B I2C Port 1 P2 P4 Muxaddr 2 0 default I2C addr 0x70 Addr 0x10 Addr 0x04 Addr 0x61 P3 I2C M 2 Socket TCA9517 Side A Side B Figure 4 Local I2C architecture The slave addresses are shown in Figure 3 and the table below Slave S...

Page 10: ...on LED5 GREEN Displays solid green when 1 8V rail is present LED6 GREEN Displays solid green when 1 1V rail is present 7 4 2 Front panel LEDs RTM311 has 3 front panel status LEDs The LEDs functionality is explained in the table below LED s front panel label Colour Description VPXRST RED Displays solid red when RESET button is pressed VPX board is reset ACT GREEN Displays solid green when both Ethe...

Page 11: ...le ended GA3 GA2 GND 12V_AUX GND GA1 GA0 POS_RP0 7 Differential TCK GND TDO TDI GND TMS TRST POS_RP0 8 Differential GND REF_CLK REF_CLK GND RES_BUS RES_BUS GND POS_RP0 9 Differential Gdiscrete1 GND FPGA TX0 FPGA TX0 GND FPGA RX0 FPGA RX0 POS_RP0 10 Differential GND FPGA TX1 FPGA TX1 GND FPGA RX1 FPGA RX1 GND POS_RP0 11 Differential P1 VBAT GND FPGA TX2 FPGA TX2 GND FPGA RX2 FPGA RX2 POS_RP0 12 Dif...

Page 12: ... System Management If connected this will pull SM 3 0 up to 3V3 12V_AUX Auxiliary Power Supplies Not connected SYSRESET System Reset Can be driven from the CPLD SYS_CON System Slot Connects to CPLD and to 4 7k pull up REF_CLK Reference Clock 25 MHz or 100 MHz Not connected NVMRO Non Volatile Memory Read Only Connects to the CPLD TCK TMS TRST TDI TDO wafer 7 JTAG Signals JTAG chain through front pa...

Page 13: ...GA LVDS3 FPGA LVDS3 GND POS_RP 1 5 Differe ntial USB2 0_ DM GND LOCAL I2C_SCL LOCAL I2C_SDA GND ZYNQ SDIO CLK ZYNQ SDIO CMD POS_RP 1 6 Differe ntial GND ZYNQ SDIO D0 ZYNQ SDIO D1 GND ZYNQ SDIO D2 ZYNQ SDIO D3 GND POS_RP 1 7 Differe ntial Maskable reset GND UTP2_RX UTP2_RX GND UTP2_TX UTP2_TX POS_RP 1 8 Differe ntial GND UTP1_RX UTP1_RX GND UTP1_TX UTP1_TX GND POS_RP 1 9 Differe ntial GND DP0 DP0 G...

Page 14: ...00BASE KX BX receive data 1000BASE X Marvell Ethernet PHY 1 UTP2_TXp n 1000BASE KX BX transmit data 1000BASE X Marvell Ethernet PHY 2 UTP2_RXp n 1000BASE KX BX receive data 1000BASE X Marvell Ethernet PHY 2 LOCAL I2C_SCL I2C clock 1 8V open drain I2C switch LOCAL I2C_SDA I2C data 1 8V open drain I2C switch ZYNQ SDIO P1 connector differential pairs 3 3V ZYNQ uSD card interface 3 3V can be used as b...

Page 15: ...cable is a customised break out cable shown below Each cable end has its own ID label The RTM31x Debug end is to connect to RTM311 via its front panel s µHDMI Debug connector The other ends provide means for debugging with pin assignments shown in the table below COM0 via a 9 Way Male D type connector Pin VPX signal name 2 FPGA LVDS1 3 GND 5 FPGA LVDS1 COM1 via a 9 Way Male D type connector Pin VP...

Page 16: ..._DISC1 Reserved 2 GPIO_DISC0 Reserved 3 GPIO_I2C_SDA 4 GPIO_I2C_SCL 5 GND 7 5 2 3 USB2 0 connector RTM311 has a USB3 0 hub which accommodates the use of both the USB2 0 and USB3 0 interfaces The USB2 0 interface is connected to VPX backplane per table below USB2 0 connector VPX backplane signals Pin1 Vcc Vs3 Pin2 DATA_N USB2 0_DM Pin3 DATA_P USB2 0_DP Pin4 GND GND 7 5 2 4 USB3 0 connector Ensure t...

Page 17: ...ce on the VP881 Contact Abaco sales for more information on the roll out schedule of an updated Zynq MPSoC BSP for VP881 that fully supports DisplayPort 7 5 2 6 Ethernet connectors RTM311 has 2 x 1Gbit ETH interfaces The ETH PHY is Marvell 88E1512 A0 NNP2I000 The ports of the PHYs connect to the VPX connector as shown below ETH PHY VPX backplane signals S1_IN_P N UTP1_RX_P N S1_OUT_P N UTP1_TX_P N...

Page 18: ...3V 4 TMS input 6 TCK input 8 TDO output 10 TDI input 13 PGND has 4 7K pull up to 3 3V and when pulled down the JTAG connector JTAG interface becomes active and the VPX JTAG interface is disabled 14 HALT not connected 3 5 7 9 11 Ground Figure 5 JTAG connector pinout 7 5 3 2 QTE connector QTE 060 03 FL D A TR RTM311 provides access to VPX backplane s differential signals via a QTE connectors The sig...

Page 19: ...TX6 41 43 FPGA RX7 FPGA RX7 42 44 FPGA TX7 FPGA TX7 47 LOCAL I2C_SDA See note below 48 LOCAL I2C_SCL See note below 50 52 QSE_DP0_P N 49 51 QSE_DP1_P N 54 56 QSE_DP2_P N 53 55 QSE_DP3_P N 58 60 QSE_DP4_P N 57 59 QSE_DP5_P N 62 64 QSE_DP6_P N 61 63 QSE_DP7_P N 66 68 QSE_DP8_P N 65 67 QSE_DP9_P N 70 72 QSE_DP10_P N 69 71 QSE_DP11_P N 74 76 QSE_DP12_P N 73 75 QSE_DP13_P N 78 80 QSE_DP14_P N 77 79 QSE...

Page 20: ... 6 Pin1 and Pin2 location in yellow and standoffs location circled in pink Figure 7 SAMTEC mating connector with place for screws circled in pink To connect to the QTE connector Use a mating connector from SAMTEC with break out direction towards VPX connectors shown as a green arrow in Figure 6 Ensure to check the signals assignment in Table 6 and pins location in Figure 6 above Place the mating c...

Page 21: ...y the top side of the M 2 module by observing the ground pads shown in Figure 8 and Figure 9 Insert the M 2 module into the M 2 connector shown in Figure 10 with the top side facing upwards Use an M2x 2 5mm screw to secure the M 2 module to the on board standoff shown in Figure 10 Figure 8 Top side of an M 2 module identified by a smaller area of the ground pad circled in green Figure 9 Bottom sid...

Page 22: ...module is the Western Digital WDS250G1B0B VPX backplane connects to both standard SATA and M 2 devices as shown in Figure 11 below Figure 11 Connections between VPX backplane and SATA M 2 connectors RTM311 provides reference clock 100MHz to the M 2 modules VPX backplane can control monitor the M 2 device via on board CPLD as below Also see Appendix A CPLD Register map for more details ...

Page 23: ...nect to LOCAL I2C_SCL and LOCAL I2C_SDA when the I2C switch Port 3 is connected M2_I2C_ALRT Status Alert signal from M 2 device when I2C interface needs attention 7 5 3 4 Standard SATA connector Molex 067800 5005 On board SATA interface can be accessed by setting SW3 OFF Note that there is no mounting hardware and SATA s power connector provided on the RTM311 for SATA connection The signals assign...

Page 24: ...ge 24 of 28 7 5 3 5 SM bus header VPX backplane s SM bus interface can be monitored using the on board SM bus header Molex 53398 0671 See the signal assignment in the table below SM bus header VPX backplane signal 1 3 3V_AUX 2 GND 3 SM0 4 SM1 5 SM2 6 SM3 ...

Page 25: ...ces Buffer inputs from switches and output to appropriate components 7 7 Battery ML 2020 3V 45mAh rechargeable battery can be fitted on board to provide a supply voltage to P1 VBAT see Table 2 in section 7 5 1 P1 VBAT description Voltage V Nominal Voltage 3 00 Maximum Voltage 3 50 Minimum Voltage 2 55 7 8 Safety This module presents no hazard to the user Users should be cautions that the PCB can h...

Page 26: ...UM082 RTM311 User Manual r1 3 UM082 www abaco com page 26 of 28 7 11 Ordering Information For ordering information contact Abaco sales and refer to the Part Number and Compatibility document ...

Page 27: ... hub Bit 4 Reset ETH PHY1 Bit 5 Reset ETH PHY2 Bit 6 7 Reserved 0x02 R W Command Register 2 Bit 0 Configure M 2 device to SATA or PCIe 1 PCIe 0 SATA Default Bit 1 Enable M 2 device s sleep mode Bit 2 Enable I2C mode in DisplayPort driver Bit 3 Enable SM bus mode in SATA driver Bit 4 7 Reserved 0x03 RO Interrupt Register Bit 0 Interrupt from ETH PHY1 Bit 1 Reserved Bit 2 M 2 s I2C alert Bit 3 7 Res...

Page 28: ...TM311 User Manual r1 3 UM082 www abaco com page 28 of 28 Register R W Description Bit 4 M 2 device activity Bit 5 Loss of data from standard SATA driver Bit 6 VPX backplane is connected SYS_CON Bit 7 Reserved ...

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