Aaeon SBC-556/L, Manual

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Chapter 3 Award BIOS Setup 57
This section allows you to configure the system based on the
specific features of the installed chipset. This chipset manages
bus speeds and access to system memory resources, such as
DRAM and the external cache. It also coordinates communica-
tions between the conventional ISA bus and the PCI bus. It must
be stated that these items should never need to be altered. The
default settings have been chosen because they provide the best
operating conditions for your system.
The only time you might consider making any changes would be if
you discovered that data was being lost while using your system.
Auto Configuration
Set this item to Enabled to pre-defined values for DRAM,
cache.. timing according to CPU type & system clock. Thus, each
item value may display differently depending on your system
configurations.
When this item is enabled, the pre-defined items will become
SHOW-ONLY.
System BIOS Cacheable
When enabled, accesses to the system BIOS ROM addressed at
F0000H-FFFFFH are cached, provided that the cache controller
is enabled.
Video BIOS Cacheable
As with caching the System BIOS above, enabling the Video BIOS
cache will cause access to video BIOS addressed at C0000H to
C7FFFH to be cached, if the cache controller is also enabled.