Aaeon PICO-APL1 User Manual Download Page 83 | Manualshive

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Appendix C – Electrical Specifications for I/O Ports

70

Pico
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PIC
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Inverter

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721-94-

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9

5

16553051

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1 x SATA

Connector,

180D. (M),

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PWR

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Box, 2P, 180D.

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721-81-

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222-97

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Front

Panel

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180D.(M).2.0

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222-97

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Audio

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8

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53

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Summary of Contents for PICO-APL1

Page 1: ...Last Updated June 21 2017 PICO APL1 PICO APL1 Single Board Computer User s Manual 1st Ed...

Page 2: ...this manual is intended to be accurate and reliable However the original manufacturer assumes no responsibility for its use or for any infringements upon the rights of third parties that may result f...

Page 3: ...their respective owners Microsoft Windows is a registered trademark of Microsoft Corp ITE is a trademark of Integrated Technology Express Inc IBM PC AT PS 2 and VGA are trademarks of International Bu...

Page 4: ...t please make sure the following items have been shipped Item Quantity PICO APL1 1 Product DVD with drivers 1 Heat Spreader optional 1 COM Line out Cable optional 1 If any of these items are missing o...

Page 5: ...ailed descriptions and explanations on the product s hardware and software features if any its specifications dimensions jumper connector settings definitions and driver installation instructions if a...

Page 6: ...sient over voltage 7 Always disconnect this device from any AC supply before cleaning 8 While cleaning use a damp cloth instead of liquid or spray detergents 9 Make sure the device is installed near a...

Page 7: ...ntrusion to the device iii Exposure to moisture iv Device is not working as expected or in a manner as described in this manual v The device is dropped or damaged vi Any obvious signs of damage displa...

Page 8: ...sion if the battery is incorrectly replaced Replace only with the same or equivalent type recommended by the manufacturer Dispose of used batteries according to the manufacturer s instructions and you...

Page 9: ...Preface IX Pico ITX Board PICO APL1 China RoHS Requirements CN AAEON Main Board Daughter Board Backplane Pb Hg Cd Cr VI PBB PBDE O SJ T 11363 2006 X SJ T 11363 2006...

Page 10: ...l Ethers PBDE PCB Other Components O O O O O Wires Connectors for External Connections O O O O O O O The quantity of poisonous or hazardous substances or elements found in each of the component s part...

Page 11: ...3 4 LVDS Port Backlight Inverter Voltage Selection Selection JP2 2 4 6 11 2 3 5 LVDS Port Backlight Lightness Control Mode JP3 12 2 4 List of Connectors 12 2 4 1 Digital IO Port CN1 14 2 4 2 LVDS Port...

Page 12: ...nd Initialization 35 3 2 AMI BIOS Setup 36 3 3 Setup Submenu Main 37 3 4 Setup Submenu Advanced 38 3 4 1 CPU configuration 40 3 4 2 SATA Configuration 41 3 4 3 Hardware Monitor 42 3 4 4 SIO Configurat...

Page 13: ...Programming 59 A 1 Watchdog Timer Registers 60 A 2 Watchdog Sample Program 61 Appendix B I O Information 64 B 1 I O Address Map 65 B 2 Memory Address Map 66 B 3 IRQ Mapping Chart 67 Appendix C Mating...

Page 14: ...Pico ITX Board PICO APL1 Chapter 1 Chapter 1 Product Specifications...

Page 15: ...Chipset Intel Pentium N4200 Celeron N3350 integrated BIOS AMI SPI Wake On LAN Yes Watchdog Timer 255 levels Power Requirement DC 12 V Power Supply Type AT ATX default lockable connector optional Syst...

Page 16: ...4bit up to 1920 x1200 60Hz select by BIOS or jumper HDMI up to 3840 x 2160 30Hz Or DDI by BIO Board optional I O Storage SATA 6 0Gb s x 1 mSATA Default MiniCard x 1 Ethernet HD Audio Codec RealteK ALC...

Page 17: ...Pico ITX Board PICO APL1 Chapter 2 Chapter 2 Hardware Information...

Page 18: ...formation 5 Pico ITX Board PICO APL1 2 1 Dimensions Component Side MATERIAL SPEC SCALE UNIT MM FINISH 0 0 1 10 0 2 50 0 3 200 0 5 500 0 8 0 5 X ANGLE TOL 1 A 2 3 4 5 6 7 8 9 10 11 B C D E F G NA t 1 6...

Page 19: ...ME MATERIAL SPEC SCALE UNIT MM FINISH APPROVED 0 0 1 10 0 2 50 0 3 200 0 5 500 0 8 0 5 X ANGLE TOL CHECKED DESIGNED DWG No ITEM DATE REMARK SHEET MODEL No PART No 1 A3 E F G H I J 2 3 NA t 1 6mm PCB 1...

Page 20: ...Chapter 2 Hardware Information 7 Pico ITX Board PICO APL1 Rear I O Configuration...

Page 21: ...ion 8 Pico ITX Board PICO APL1 2 2 Jumpers and Connectors Component Side MATERIAL SPEC SCALE UNIT MM FINISH 0 0 1 10 0 2 50 0 3 200 0 5 500 0 8 0 5 X ANGLE TOL 1 A 2 3 4 5 6 7 8 9 10 11 B C D E F G NA...

Page 22: ...ME MATERIAL SPEC SCALE UNIT MM FINISH APPROVED 0 0 1 10 0 2 50 0 3 200 0 5 500 0 8 0 5 X ANGLE TOL CHECKED DESIGNED DWG No ITEM DATE REMARK SHEET MODEL No PART No 1 A3 E F G H I J 2 3 NA t 1 6mm PCB 1...

Page 23: ...the board s jumpers that you can configure for your application Label Function JP1 1 3 5 Clear CMOS Jumper JP1 2 4 6 Auto Power Button Enable Disable Selection JP2 1 3 5 LVDS Port Operating Voltage Se...

Page 24: ...per JP1 1 3 5 Normal Default Clear CMOS 2 3 2 Auto Power Button Enable Disable Selection JP1 2 4 6 Enable Default Disable 2 3 3 LVDS Port Operating Voltage Selection JP2 1 3 5 5V 3 3V Default 2 3 4 LV...

Page 25: ...ou can configure for your application Label Function CN1 Digital IO Port CN2 LVDS Port Inverter Backlight Connector CN3 Front Panel CN4 Mini Card Slot Half Mini Card CN5 SPI Programming Header CN6 Min...

Page 26: ...Chapter 2 Hardware Information 13 Pico ITX Board PICO APL1 CN17 COM Port 1 2 line out connector CN18 LPC Port CN19 USB 2 0 Port 1...

Page 27: ...ort CN1 Pin Pin Name Signal Type Pin Name 1 5V PWR 5V 2 DIO0 I O 5V 3 DIO1 I O 5V 4 DIO2 I O 5V 5 DIO3 I O 5V 6 GND GND 2 4 2 LVDS Port Inverter Backlight Connector CN2 Pin Pin Name Signal Type Signal...

Page 28: ...4 GND GND 5 BKL_ENABLE OUT 3 3V LVDS BKL_PWR can be set to 5V or 12V by JP2 LVDS BKL_CONTROL can be set by JP3 The driving current supports up to 2A 2 4 3 Front Panel CN3 Pin Pin Name Pin Pin Name 1...

Page 29: ...ot Half Mini Card CN4 Pin Pin Name Signal Type Signal Level 1 PCIE_WAKE IN 2 3 3VSB PWR 3 3V 3 NC 4 GND GND 5 NC 6 1 5V PWR 1 5V 7 PCIE_CLK_REQ IN 8 NC PWR 9 GND GND 10 NC I O 11 PCIE_REF_CLK DIFF 12...

Page 30: ...ND 22 PCIE_RST OUT 3 3V 23 PCIE_RX DIFF 24 3 3VSB PWR 3 3V 25 PCIE_RX DIFF 26 GND GND 27 GND GND 28 1 5V PWR 1 5V 29 GND GND 30 SMB_CLK I O 3 3V 31 PCIE_TX DIFF 32 SMB_DATA I O 3 3V 33 PCIE_TX DIFF 34...

Page 31: ...3VSB PWR 3 3V 42 NC 43 GND GND 44 NC 45 NC 46 NC 47 NC 48 1 5V PWR 1 5V 49 NC 50 GND GND 51 NC 52 3 3VSB PWR 3 3V 2 4 5 BIO connector CN7 Pin Pin Name Pin Pin Name 1 12VSB 2 GND 3 GND 4 PCIE_TXN0 5 P...

Page 32: ...4 GND 15 GND 16 PS_ON 17 NC 18 NC 19 5VSB 20 5VSB 21 5VSB 22 5VSB 23 PCIE_REF_CLK0 24 RESET 25 PCIE_REF_CLK0 26 GND 27 GND 28 NC 29 NC 30 NC 31 NC 32 GND 33 GND 34 NC 35 NC 36 NC 37 NC 38 GND 39 GND 4...

Page 33: ..._CLK 54 GND 55 SMB_DATA 56 WAKE 57 GND 58 USB_OC0 59 5V 60 USB_OC1 61 5V 62 5V 63 5V 64 5V 65 LPC_AD0 66 LPC_FRAME 67 LPC_AD1 68 SERIRQ 69 LPC_AD2 70 LPC_DRQ 71 LPC_AD3 72 GPIO0 73 GND 74 AGND 75 LPC_...

Page 34: ...Pin Name Signal Type Signal Level 1 GND GND 2 SATA_TX1 DIFF 3 SATA_TX1 DIFF 4 GND GND 5 SATA_RX1 DIFF 6 SATA_RX1 DIFF 7 GND GND 2 4 7 Battery CN9 Pin Pin Name Signal Type Signal Level 1 3 3V PWR 3 3V...

Page 35: ...DIFF 2 MDI0 DIFF 3 MDI1 DIFF 4 MDI2 DIFF 5 MDI2 DIFF 6 MDI1 DIFF 7 MDI3 DIFF 8 MDI3 DIFF 2 4 9 USB3 0 Ports 0 and 1 CN11 Pin Pin Name Signal Type Signal Level 1 5VSB PWR 5V 2 USB0_D DIFF 3 USB0_D DIFF...

Page 36: ...Board PICO APL1 11 USB1_D DIFF 12 USB1_D DIFF 13 GND GND 14 USB1_SSRX DIFF 15 USB1_SSRX DIFF 16 GND GND 17 USB1_SSTX DIFF 18 USB1_SSTX DIFF 2 4 10 5V Output for SATA HDD CN12 Pin Pin Name Signal Type...

Page 37: ...MI Port CN13 Pin Pin Name Signal Type Signal level 1 TMDS_DAT2 DIFF 2 GND GND 3 TMDS_DAT2 DIFF 4 TMDS_DAT1 DIFF 5 GND GND 6 TMDS_DAT1 DIFF 7 TMDS_DAT0 DIFF 8 GND GND 9 TMDS_DAT0 DIFF 10 TMDS_CLK DIFF...

Page 38: ...V I O 5V 19 HPLG_DETECT IN 2 4 12External 12V Input CN14 Pin Pin Name Signal Type Signal Level 1 121V PWR 12V 2 GND GND 2 4 13DDR3L SO DIMM Slot CN15 Standard specification 2 4 14LVDS Port CN16 LVDS L...

Page 39: ...LVDS_A_CLK DIFF 6 LVDS_A_CLK DIFF 7 LCD_PWR PWR 3 3V 5V 8 GND GND 9 LVDS_DA0 DIFF 10 LVDS_DA0 DIFF 11 LVDS_DA1 DIFF 12 LVDS_DA1 DIFF 13 LVDS_DA2 DIFF 14 LVDS_DA2 DIFF 15 LVDS_DA3 DIFF 16 LVDS_DA3 DIF...

Page 40: ...25 LVDS_DB3 DIFF 26 LVDS_DB3 DIFF 27 LCD_PWR PWR 3 3V 5V 28 GND GND 29 LVDS_B_CLK DIFF 30 LVDS_B_CLK DIFF 2 4 15COM Port 1 2 line out connector CN17 Pin Pin Name Signal Type Signal Level 1 DCDB IN 2 D...

Page 41: ...l Type Signal Level 9 DCDA IN 10 DSRA IN 11 RXA IN 12 RTSA OUT 9V 13 TXA OUT 9V 14 CTSA IN 15 DTRA OUT 9V 16 RIA IN 17 GND GND 18 AGND GND 19 LOUT_R I O 20 LOUT_L I O 2 4 16COM port2 RS 485 Pin Pin Na...

Page 42: ...port2 RS 422 Pin Pin Name Signal Type Signal Level 1 RS422_TX OUT 5V 2 NC 3 RS422_TX OUT 5V 4 NC 5 RS422_RX IN 6 NC 7 RS422_RX IN 8 NC 5V 12V PWR 5V 12V 9 GND GND COM2 RS 232 422 485 can be set by BIO...

Page 43: ...Signal Level 1 LAD0 I O 3 3V 2 LAD1 I O 3 3V 3 LAD2 I O 3 3V 4 LAD3 I O 3 3V 5 3 3V PWR 3 3V 6 LFRAME IN 7 LRESET OUT 3 3V 8 GND GND 9 LCLK OUT 10 LDRQ0 IN 11 LDRQ1 IN 12 SERIRQ I O 3 3V 2 4 19USB 2 0...

Page 44: ...for I O Port I O Reference Signal Name Rate Output Digital IO Port CN1 D0 D3 5V Open drain LVDS Port Inverter Backlight Connector CN2 VDD 5V 2A or 12V 2A Mini Card Slot CN4 3 3VSB 1 5V 3 3V 1 1A 1 5V...

Page 45: ...Chapter 2 Hardware Information 32 Pico ITX Board PICO APL1 COM Port 2 CN17 5V 12V 5V 1A or 12V 1A LPC Port CN18 3 3V 3 3V 0 5A USB 2 0 Port 1 CN19 5VSB 5VSB 0 5A...

Page 46: ...Chapter 2 Hardware Information 33 Pico ITX Board PICO APL1 2 4 21 Function Block...

Page 47: ...Pico ITX Board PICO APL1 Chapter 3 Chapter 3 AMI BIOS Setup...

Page 48: ...MOS memory and BIOS NVRAM If system configuration is not found or system configuration data error is detected system will load optimized default and re boot with this default system configuration auto...

Page 49: ...at it retains the Setup information when the power is turned off Entering Setup Power on the computer and press Del or ESC immediately This will allow you to enter Setup Main Set the date use tab to s...

Page 50: ...d PICO APL1 3 3 Setup Submenu Main Press Delete to enter Setup Options summary default setting System Date Day MM DD YYYY Change the month year and century The Day is changed automatically System Time...

Page 51: ...mary default setting CPU Configuration CPU Configuration Parameters SATA Configuration SATA Device Configuration USB Configuration USB Configuration Parameters SIO Configuration SIO Chip configuration...

Page 52: ...Chapter 3 AMI BIOS Setup 39 Pico ITX Board PICO APL1 Power Management System ACPI Power Mode Wake Event Configuration Digital IO Port Configuration Set Input Output of digital Port Configuration...

Page 53: ...lt Failsafe Default Enable Disable Intel SpeedStep Intel Virtualization Technology Disabled Enabled Optimal Default Failsafe Default When enabled a VMM can utilize the additional hardware capabilities...

Page 54: ...Chapter 3 AMI BIOS Setup 41 Pico ITX Board PICO APL1 3 4 2 SATA Configuration Options summary Port 0 1 Disabled Enabled Optimal Default Failsafe Default Enable Disable SATA port...

Page 55: ...Chapter 3 AMI BIOS Setup 42 Pico ITX Board PICO APL1 3 4 3 Hardware Monitor...

Page 56: ...p 43 Pico ITX Board PICO APL1 3 4 4 SIO Configuration Options summary default setting Serial Port 1 2 Configuration View and Set Basic properties of the SIO Logical device Like IO Base IRQ Range DMA C...

Page 57: ...lt Enable or Disable this Logical Device Possible Use Automatic Settings Optimal Default Failsafe Default IO 2F8h IRQ 3 IO 3F8h IRQ 4 Allows user to change Device s Resource settings New settings will...

Page 58: ...Chapter 3 AMI BIOS Setup 45 Pico ITX Board PICO APL1 Options summary DIO Output Input Set DIO as Input or Output Level High Optimal Default Failsafe Default Low Set output level when DIO pin is output...

Page 59: ...Options summary Power Mode ATX Type Optimal Default Failsafe Default AT Type Select system power mode Restore AC Power Loss Last State Optimal Default Failsafe Default Always On Always Off RTC wake s...

Page 60: ...Chapter 3 AMI BIOS Setup 47 Pico ITX Board PICO APL1 3 4 7 Setup submenu Chipset...

Page 61: ...Chapter 3 AMI BIOS Setup 48 Pico ITX Board PICO APL1 3 4 8 North Bridge...

Page 62: ...onfiguration Options summary LVDS Disabled Enabled Optimal Default Failsafe Default Enable Disabled this panel LVDS Panel Type 640X480 60HZ 800X480 60HZ 800X600 60HZ 1024X600 60HZ 1024X768 60HZ Optima...

Page 63: ...3 AMI BIOS Setup 50 Pico ITX Board PICO APL1 1366X768 60HZ 1440X900 60HZ 1600X1200 60HZ 1920X1080 60HZ 1920X1200 60HZ Select LCD panel used by Internal Graphics Device by selecting the appropriate set...

Page 64: ...t Type Normal Optimal Default Failsafe Default Inverted Select backlight control signal type Backlight Level 0 10 20 30 40 50 60 70 80 Optimal Default Failsafe Default 90 100 Select backlight control...

Page 65: ...CO APL1 3 5 1 South Bridge Options summary HD Audio Support Disabled Enabled Optimal Default Failsafe Default Enable Disabled HD audio PCIe Speed Auto Optimal Default Failsafe Default Gen1 Gen2 Config...

Page 66: ...tems and press Enter a dialog box appears which lets you enter a password You can enter no more than six letters or numbers Press Enter after you have typed in the password A second dialog box asks yo...

Page 67: ...safe Default EnableDisable showing boot logo Monitor Mwait Disable Enabled Auto Optimal Default Failsafe Default Enable Disable Monitor Mwait To install Linux OS please set this item to disable Ipv4 P...

Page 68: ...Chapter 3 AMI BIOS Setup 55 Pico ITX Board PICO APL1 3 6 Setup submenu Exit...

Page 69: ...Pico ITX Board PICO APL1 Chapter 4 Chapter 4 Drivers Installation...

Page 70: ...nce below to install the drivers Step 1 Install Chipset Driver 1 Open the STEP1 CHIPSET folder and open the SetupChipset exe file 2 Follow the instructions 3 Drivers will be installed automatically St...

Page 71: ...Open the STEP5 TXE folder and open the SetupTXE exe file 2 Follow the instructions 3 Driver will be installed automatically Step 6 Install FintekSerial_Patch_T4R8 Driver 1 Open the STEP6 FintekSerial_...

Page 72: ...Pico ITX Board PICO APL1 Appendix A Appendix A Watchdog Timer Programming...

Page 73: ...nable Disable time out output via WDTRST 0 Disable 1 Enable Pulse Width 0x05 0 1 01 Width of Pulse signal 00 1ms do not use 01 25ms 10 125ms 11 5s Pulse width is must longer then 16ms Signal Polarity...

Page 74: ...r define PSWidthBit 0x00 WDTRST Pulse width Bit0 1 define PSWidthVal 0x01 25ms for WDTRST pulse define PolarityBit 0x02 WDTRST Signal polarity Bit2 define PolarityVal 0x00 Low active for WDTRST define...

Page 75: ...DTEnable VOID AaeonWDTEnable WDTEnableDisable 1 Procedure AaeonWDTConfig VOID AaeonWDTConfig byte Counter BOOLEAN Unit Disable WDT counting WDTEnableDisable 0 Clear Watchdog Timeout Status WDTClearTim...

Page 76: ...s 25ms WDTSetBit TimerReg PSWidthBit PSWidthVal Watchdog WDTRST Enable WDTSetBit DevReg WDTRstBit WDTRstVal VOID WDTClearTimeoutStatus WDTSetBit TimerReg StatusBit 1 VOID WDTWriteByte byte Register by...

Page 77: ...Pico ITX Board PICO APL1 Appendix B Appendix B I O Information...

Page 78: ...Appendix B I O Information 65 Pico ITX Board PICO APL1 B 1 I O Address Map...

Page 79: ...Appendix B I O Information 66 Pico ITX Board PICO APL1 B 2 Memory Address Map...

Page 80: ...Appendix B I O Information 67 Pico ITX Board PICO APL1 B 3 IRQ Mapping Chart...

Page 81: ...Pico ITX Board PICO APL1 Appendix C Appendix C Mating Connectors...

Page 82: ...Cable P N HDMI 1 x HDMI FOXCON N QJ51191 LFB4 7 F 19 16544019 32 N A COM Port 2 x COMs 1x Line out Cable WL125 3H 20P 1 25mm Housing Dua l DB9 M Line Out Jack 15cm PINREX 712 94 20TWR 8 20 16558201 0...

Page 83: ...SATA PWR 1 x Wafer Box 2P 180D M DIP 2 0mm PINREX 721 81 02TW0 0 2 16553020 25 170215015 5 Power Conn TERMINAL 2 P 1 90D M D IP Dinkle DT 126 VP S20 16002P 2 16526021 05 Digital I O 1 x WAFER BOX 6P 1...

Page 84: ...Pico ITX Board PICO APL1 Housing Dua l DB9 M Line Out Jack 15cm USB 1 x Wafer Box 5P 180D M SMD 1 25m m CATCH 1201 70 0 05SM 5 16559050 37 17000502 07 BIO Board Board Connector 80 P 180D F Hir ose FX1...

Page 85: ...Pico ITX Board PICO APL1 Appendix D Appendix D DIO...

Page 86: ...1 provides one serial access interface I2C Bus to read write internal registers The address of Serial Bus is 0x6E 0110_1110 The related register for configuring DIO is list as follows Configuration an...

Page 87: ...PICO APL1 The following is a sample code for 8 input MODEL SMALL CODE begin mov cl 01h mov al 80h call CT_I2CWriteByte call Delay5ms mov al 00h mov cl 20h call CT_I2CWriteByte mov cl 22h call CT_I2CR...

Page 88: ...it Slave Address Register inc ch Set the slave address and mov al ch prepare for a READ command out dx al mov dx F040h 05h Host Command Register mov al cl offset to read out dx al mov dx F040h 06h xor...

Page 89: ...x F040h 00h Host Control Register xor al al Clear previous commands out dx al call Delay5ms mov dx F040h 04h Transmit Slave Address Register mov al ch Set the slave address and out dx al prepare for a...

Page 90: ...dp Wait until the busy bit clears indicating that the SMBUS activity has concluded CT_Chk_SMBus_Ready Proc Near mov dx F040h 01h Host Status Register Check_I2C_ByteRead_ForBusy in al dx test al 08h jn...

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