Aaeon PCM-4897, User Manual

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76 PCM-4897 User Manual
The displayed configuration is based on the manufacturer's SETUP
DEFAULTS settings.
This section allows you to configure the system based on the
specific features of the installed chipset. This chipset manages bus
speeds and access to system memory resources, such as SDRAM.
It also coordinates communications between the conventional ISA
bus and the PCI bus. It must be stated that these items should
never need to be altered. The default settings have been chosen
because they provide the best operating conditions for your
system. The only time you might consider making any changes
would be if you discovered that data was being lost while using
your system.
Because of the complexity and technical nature of some of the
options, not all of the options are described here.
SDRAM CAS Latency Time
When synchronous DRAM is installed, you can control the
number of CLKs between when the SDRAMs sample a read
command and when the contoller samples read data from the
SDRAMs. Do not reset this field from the default value specified
by the system designer.
8/16 Bit I/O Recovery Time
The I/O recovery mechanism adds bus clock cycles between PCI-
originated I/O cycles to the ISA bus. This delay takes place
because the PCI bus is so much faster than the ISA bus.
These two fields let you add recovery time (in bus clock cycles) for
16-bit and 8-bit I/O.