Aaeon GENE-APL5 User Manual Download Page 119 | Manualshive

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Appendix B – Electrical Specifications for I/O Ports

105

3.5

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ub

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act

Bo

ard

G

ENE

-AP

L5

Connector

Label

Function

Mating Connector

Available

Cable

Cable P/N

Vendor

Model No

CN10

LPT or Digital

I/O Connector

Molex

51110-2650

Parallel Port

Cable

1701260200

CN11

LPC Connector JST

SHR-12V-S-B

AAEON LPC

Cable

1703120130

CN12

COM Port #3

Connector

Molex

51021-0900

Serial Port

Cable

1701090150

CN14

COM Port #4

Connector

Molex

51021-0900

Serial Port

Cable

1701090150

CN15

PS/2 KB/MS

Connector

JST

PHDR-06VS

PS/2 KB/MS

Cable

1700060152

CN16

USB Port #2

Connector

Molex

51021-0500

USB Cable 1700050207

CN17

USB Port #3

Connector

Molex

51021-0500

USB Cable 1700050207

CN19

USB Port #4

Connector

Molex

51021-0500

USB Cable 1700050207

CN20

USB Port #5

Connector

Molex

51021-0500

USB Cable 1700050207

CN21

LVDS Port2

Connector

HIROSE DF13-30DS-1.25C N/A

N/A

CN22

Touch Screen

Connector

JST

SHR-9V-S-B

N/A

N/A

CN23

CPU Fan

Connector

Molex

22-01-2035

N/A

N/A

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Summary of Contents for GENE-APL5

Page 1: ...Last Updated November 16 2021 GENE APL5 3 5 Subcompact Board User s Manual 5th Ed ...

Page 2: ...d in this manual is intended to be accurate and reliable However the original manufacturer assumes no responsibility for its use or for any infringements upon the rights of third parties that may result from its use The material in this document is for product information only and is subject to change without notice While reasonable efforts have been made in the preparation of this document to ass...

Page 3: ...ark of Microsoft Corp Intel Pentium Celeron and Xeon are registered trademarks of Intel Corporation Intel Core and Intel Atom are trademarks of Intel Corporation ITE is a trademark of Integrated Technology Express Inc IBM PC AT PS 2 and VGA are trademarks of International Business Machines Corporation All other product names or trademarks are properties of their respective owners ...

Page 4: ...ing List Before setting up your product please make sure the following items have been shipped Item Quantity GENE APL5 MB 1 Heatsink 1 If any of these items are missing or damaged please contact your distributor or sales representative immediately ...

Page 5: ...d descriptions and explanations on the product s hardware and software features if any its specifications dimensions jumper connector settings definitions and driver installation instructions if any to facilitate users in setting up their product Users may refer to the product page at AAEON com for the latest version of this document ...

Page 6: ...transient over voltage 7 Always disconnect this device from any AC supply before cleaning 8 While cleaning use a damp cloth instead of liquid or spray detergents 9 Make sure the device is installed near a power outlet and is easily accessible 10 Keep this device away from humidity 11 Place the device on a solid surface during installation to prevent falls 12 Do not cover the openings on the device...

Page 7: ...usion to the device iii Exposure to moisture iv Device is not working as expected or in a manner as described in this manual v The device is dropped or damaged vi Any obvious signs of damage displayed on the device 18 DO NOT LEAVE THIS DEVICE IN AN UNCONTROLLED ENVIRONMENT WITH TEMPERATURES BEYOND THE DEVICE S PERMITTED STORAGE TEMPERATURES SEE CHAPTER 1 TO PREVENT DAMAGE ...

Page 8: ...plosion if the battery is incorrectly replaced Replace only with the same or equivalent type recommended by the manufacturer Dispose of used batteries according to the manufacturer s instructions and your local government s recycling or disposal directives Attention Il y a un risque d explosion si la batterie est remplacée de façon incorrecte Ne la remplacer qu avec le même modèle ou équivalent re...

Page 9: ...质或元素名称及含量 AAEON Main Board Daughter Board Backplane 部件名称有毒有害物质或元素铅 Pb 汞 Hg 镉 Cd 六价铬 Cr VI 多溴联苯 PBB 多溴二苯醚 PBDE 印刷电路板及其电子组件外部信号连接器及线材 O 表示该有毒有害物质在该部件所有均质材料中的含量均在 SJ T 11363 2006 标准规定的限量要求以下 X 表示该有毒有害物质至少在该部件的某一均质材料中的含量超出 SJ T 11363 2006 标准规定的限量要求备注此产品所标示之环保使用期限系指在一般正常使用状况下 ...

Page 10: ...henyl Ethers PBDE PCB Other Components O O O O O Wires Connectors for External Connections O O O O O O O The quantity of poisonous or hazardous substances or elements found in each of the component s parts is below the SJ T 11363 2006 stipulated requirement X The quantity of poisonous or hazardous substances or elements found in at least one of the component s parts is beyond the SJ T 11363 2006 s...

Page 11: ...rt 1 Backlight Lightness Control Mode Selection JP2 18 2 3 4 COM2 Pin8 Function Selection JP3 18 2 3 5 COM3 Pin8 Function Selection JP4 19 2 3 6 Auto Power Button Enable Disable Selection JP5 19 2 3 7 Front Panel Connector JP6 19 2 3 8 LVDS Port 2 Backlight Inverter VCC Selection JP7 20 2 3 9 LVDS Port 2 Operating VDD Selection JP7 20 2 3 10 LVDS Port 2 Backlight Lightness Control Mode Selection J...

Page 12: ...o Port CN15 39 2 4 16 USB 2 0 Port 2 CN16 39 2 4 17 USB 2 0 Port 3 CN17 40 2 4 18 COM Port 1 CN18 Wafer Optional 40 2 4 19 USB 2 0 Port 4 CN19 41 2 4 20 USB 2 0 Port 5 CN20 42 2 4 21 LVDS Port 2 CN21 42 2 4 22 Touchscreen Connector CN22 44 2 4 23 CPU Fan CN23 Optional 46 2 4 24 LVDS Port 2 Inverter Backlight Connector CN24 47 2 4 25 USB 3 0 Ports 0 and 1 CN25 47 2 4 26 LAN RJ 45 Port 2 CN26 48 2 4...

Page 13: ...nfiguration 68 3 4 4 Hardware Monitor 70 3 4 4 1 Smart Fan Configuration 71 3 4 5 SIO Configuration 72 3 4 5 1 Serial Port 1 Configuration 73 3 4 5 2 Serial Port 2 Configuration 74 3 4 5 3 Serial Port 3 Configuration 75 3 4 5 4 Serial Port 4 Configuration 76 3 4 5 5 Parallel Port Configuration 77 3 4 6 Power Management 78 3 4 7 Digital IO Port Configuration 79 3 5 Setup Submenu Chipset 80 3 5 1 No...

Page 14: ... 4 1 Drivers Download and Installation 92 Appendix A I O Information 94 A 1 I O Address Map 95 A 2 Memory Address Map 97 A 3 IRQ Mapping Chart 98 Appendix B Mating Connectors 103 B 1 List of Mating Connectors and Cables 104 Appendix C Electrical Specifications for I O Ports 107 C 1 Electrical Specifications for I O Ports 108 ...

Page 15: ...3 5 Subcompact Board GENE APL5 Chapter 1 Chapter 1 Product Specifications ...

Page 16: ...Hz up to 2 40GHz Atom E3950 4C 4T 1 60GHz up to 2 00GHz Atom E3940 4C 4T 1 60GHz up to 1 80GHz Atom E3930 2C 2T 1 30GH up to 1 80GHz CPU TDP Pentium N4200 Celeron N3350 6W Atom E3950 12W Atom E3940 9 5W Atom E3930 6 5W Chipset Integrated with Intel SoC Memory Type DDR3L up to 1866MHz SODIMM x 1 Max Memory Capacity 8GB BIOS UEFI Wake on LAN Yes Watchdog Timer 255 Levels Security TPM 2 0 Optional RT...

Page 17: ...Intel E3950 DDR3L 1866MHz 8GB memory Display Controller Intel HD Graphics 500 505 LVDS eDP LVDS1 Dual Channel 18 24 bit x 1 LVDS2 Dual Channel 18 24 bit x 1 Optional HDMI 1 4b Display Interface VGA x 1 Multiple Display 3 Simultaneous Displays Audio Codec Realtek ALC897 892 Audio Interface Line in Line out MIC Speaker External I O Ethernet Intel i210 I211 10 100 1000Base TX RJ 45 x 2 USB USB3 2 Gen...

Page 18: ...it x 1 Optional HDMI 1 4b SATA SATA III x 1 5V SATA Power Connector x 1 Audio Audio Header x 1 DIO GPIO 8 bit SMBus I2C I2C x 1 SMBus x 1 Touch 4 5 8 wire Touch Controller x 1 Optional Fan DC Fan x 1 Optional Smart Fan SIM Micro SIM x 1 Optional Front Panel HDD LED PWR LED Power Button Buzzer Reset Others Parallel Port SPP EPP ECP x 1 optional select by BIOS Expansion Mini PCIe mSATA mSATA x 1 Ful...

Page 19: ... APL5 Mechanical Dimensions L x W 5 75 x 4 146mm x 101 7mm Environment Operating Temperature 32 F 140 F 0 C 60 C Storage Temperature 40 F 176 F 40 C 80 C Operating Humidity 0 90 relative humidity non condensing MTBF Hours 365 976 Certification EMC CE FCC Class A ...

Page 20: ...Chapter 1 Product Specifications 6 3 5 Subcompact Board GENE APL5 1 2 Function Block Diagram ...

Page 21: ...3 5 Subcompact Board GENE APL5 Chapter 2 Chapter 2 Hardware Information ...

Page 22: ...Chapter 2 Hardware Information 8 3 5 Subcompact Board GENE APL5 2 1 Dimensions Component Side ...

Page 23: ...Chapter 2 Hardware Information 9 3 5 Subcompact Board GENE APL5 Solder Side ...

Page 24: ...Chapter 2 Hardware Information 10 3 5 Subcompact Board GENE APL5 2 1 1 Dimensions Optional HDMI SKU Component Side ...

Page 25: ...Chapter 2 Hardware Information 11 3 5 Subcompact Board GENE APL5 Solder Side ...

Page 26: ...Chapter 2 Hardware Information 12 3 5 Subcompact Board GENE APL5 With Heatsink ...

Page 27: ...Chapter 2 Hardware Information 13 3 5 Subcompact Board GENE APL5 2 2 Jumpers and Connectors Component Side 0 0 10 0 50 0 200 0 500 0 0 5 ANGLE TO Component Side ...

Page 28: ... APL5 Solder Side REV NAME MATERIAL SPEC SCALE UNIT MM FINISH APPROVED 0 0 1 10 0 2 50 0 3 200 0 5 500 0 8 0 5 ANGLE TOL CHECKED DESIGNED DWG No SHEET MODEL No PART No NA t 1 8mm PCB 1 1 A1 1 GENE APL5 PCB_DRAWING Kevin Willie 1907APL504 1907APL504 Solder Side ...

Page 29: ...Chapter 2 Hardware Information 15 3 5 Subcompact Board GENE APL5 2 2 1 Jumpers and Connectors Optional HDMI SKU Component Side 0 10 50 200 500 0 ANGLE 2 3 4 5 6 7 8 9 0 1 Component Side ...

Page 30: ...APL5 Solder Side REV NAME MATERIAL SPEC SCALE UNIT MM FINISH APPROVED 0 0 1 10 0 2 50 0 3 200 0 5 500 0 8 0 5 ANGLE TOL CHECKED DESIGNED DWG No SHEET MODEL No PART No 3 NA t 1 8mm PCB 1 1 A1 1 GENE APL5 PCB_DRAWING Kevin Willie 1907APL504 1907APL504 Solder Side ...

Page 31: ... LVDS Port1 Backlight Lightness Control Mode Selection JP3 COM2 Pin8 Function Selection JP4 COM3 Pin8 Function Selection JP5 Auto Power Button Enable Disable Selection JP6 Front Panel Connector JP7 LVDS Port2 Backlight Inverter VCC Selection and Operating VDD Selection JP8 LVDS Port2 Backlight Lightness Control Mode Selection JP9 Touch Screen 4 5 8 wire Mode Selection JP10 Clear CMOS Jumper 2 3 1 ...

Page 32: ...ion JP2 VR Mode Default PWM Mode 2 3 4 COM2 Pin8 Function Selection JP3 12V Ring Default 5V 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 1 2 3 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 3 5 1 2 3 4 5 6 1 2 3 4 5 6 1 ...

Page 33: ...onnector JP6 Pin Pin Name Pin Pin Name 1 PWR_BTN 2 PWR_BTN 3 HDD_LED 4 HDD_LED 5 SPEAKER 6 SPEAKER 7 PWR_LED 8 PWR_LED 9 H W RESET 10 H W RESET 3 4 5 6 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 3 4 5 6 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 3 4 5 6 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 3 4 5 6 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 3 5 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 3 4 5 6 3 4 ...

Page 34: ... Port 2 Operating VDD Selection JP7 3 3V Default 5V Note To prevent damage to the system or unwanted operation do not use any other configuration for JP1 than what is shown in Ch2 4 1 and Ch2 4 2 2 3 10 LVDS Port 2 Backlight Lightness Control Mode Selection JP8 VR Mode Default PWM Mode 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 1 2 3 ...

Page 35: ...ardware Information 21 3 5 Subcompact Board GENE APL5 2 3 11 Touch Screen 4 5 8 Wire Selection JP9 4 8 Wire Mode Default 5 Wire Mode 2 3 12 Clear CMOS Jumper JP10 Normal Default Clear CMOS 1 2 3 1 2 3 1 2 3 1 2 3 ...

Page 36: ...nector CN3 5V Output for SATA HDD CN4 SATA Port CN5 External Power Input CN6 External 5VSB Input Optional CN7 Audio I O Port CN8 LVDS Port1 CN9 COM Port 2 CN10 LPT Port or Digital I O Port CN11 LPC Port CN12 COM Port 3 CN13 SPI Debug Port CN14 COM Port 4 CN15 PS 2 Keyboard Mouse Combo Port CN16 USB 2 0 Port 2 CN17 USB 2 0 Port 3 CN18 COM Port 1 Wafer Optional CN19 USB 2 0 Port 4 CN20 USB 2 0 Port ...

Page 37: ... Port1 CN28 COM Port 1 D SUB 9 CN29 HDMI Port Optional CN30 Battery CN31 VGA Port CN32 Micro SIM Card Socket CN33 Mini Card Slot Half Size CN34 mSATA Slot Full Size DIMM1 DDR3L SO DIMM Slot 2 4 1 5VSB Output w SMBus CN1 Pin Pin Name Signal Type Signal Level 1 SMB_DATA I O 3 3V 2 GND GND 3 SMB_CLK I O 3 3V 4 GND GND 5 PS_ON OUT 5V 6 5VSB PWR 5V SMB_DATA 1 6 GND SMB_CLK GND PS_ON 5VSB ...

Page 38: ...PWR PWR 5V 12V 2 BKL_CONTROL OUT 3 GND GND 4 GND GND 5 BKL_ENABLE OUT 5V Note 1 LVDS BKL_PWR can be set to 5V or 12V by JP1 Max current is 2A Note 2 LVDS BKL_CONTROL can be set by JP2 2 4 3 5V Output for SATA HDD CN3 Pin Pin Name Signal Type Signal Level 1 5V PWR 5V 2 GND GND Note Pin 1 max current is 2A BLK_PWR 2 3 4 5 1 BKL_CONTROL GND GND BKL_ENABLE 5V GND ...

Page 39: ... 1 GND GND 2 SATA_TX DIFF 3 SATA_TX DIFF 4 GND GND 5 SATA_RX DIFF 6 SATA_RX DIFF 7 GND GND 2 4 5 External Power Input CN5 Pin Pin Name Signal Type Signal Level 1 VIN PWR 9V 19V or 12V 2 GND GND Note 1 There are two types of power input 9V 19V or 12V only by BOM Change Note 2 Pin 1 VIN max current is 8A Pin 1 Pin 7 12V GND ...

Page 40: ...ower connector ensure the ATX power supply is fully discharged when powering off or before restarting the system Discharge time depends on the power supply and can be 3 to 5 seconds or more 2 4 7 Audio I O Port CN7 Pin Pin Name Signal Type Signal Level 1 MIC_L IN 2 MIC_R IN 3 GND_AUDIO GND 5VSB GND PS_ON 1 2 3 MIC_L 1 10 MIC_R LINE_L_IN LINE_R_IN LEFT_OUT RIGHT_OUT 5V_AUDIO GND_AUDIO GND_AUDIO GND...

Page 41: ...ND_AUDIO GND 7 LEFT_OUT OUT 8 GND_AUDIO GND 9 RIGHT_OUT OUT 10 5V_AUDIO PWR 5V 2 4 8 LVDS Port 1 CN8 Note 1 LVDS LCD_PWR can be set to 3 3V or 5V by JP1 Max current is 2A Pin Pin Name Signal Type Signal Level 1 BKL_ENABLE OUT 2 BKL_CONTROL OUT 3 LCD_PWR PWR 3 3V 5V 4 GND GND 5 LVDS_A_CLK DIFF 6 LVDS_A_CLK DIFF PIN 1 PIN 2 PIN 30 PIN 29 ...

Page 42: ..._DA0 DIFF 11 LVDS_DA1 DIFF 12 LVDS_DA1 DIFF 13 LVDS_DA2 DIFF 14 LVDS_DA2 DIFF 15 LVDS_DA3 DIFF 16 LVDS_DA3 DIFF 17 DDC_DATA I O 3 3V 18 DDC_CLK I O 3 3V 19 LVDS_DB0 DIFF 20 LVDS_DB0 DIFF 21 LVDS_DB1 DIFF 22 LVDS_DB1 DIFF 23 LVDS_DB2 DIFF 24 LVDS_DB2 DIFF 25 LVDS_DB3 DIFF 26 LVDS_DB3 DIFF 27 LCD_PWR PWR 3 3V 5V 28 GND GND 29 LVDS_B_CLK DIFF 30 LVDS_B_CLK DIFF ...

Page 43: ...2V can be set by JP3 Max current in power supply mode is 0 5A Note 2 COM2 RS 232 422 485 can be set by BIOS setting Default is RS 232 RS 232 Mode Pin Pin Name Signal Type Signal Level 1 DCD2 IN 2 DSR2 IN 3 RX2 IN 4 RTS2 OUT 5V 5 TX2 OUT 5V 6 CTS2 IN 7 DTR2 OUT 5V 8 RI2 5V 12V IN 5V 12V 9 GND GND 1 2 3 4 5 6 7 8 9 ...

Page 44: ...me Signal Type Signal Level 1 RS485_ D2 I O 5V 2 NC 3 RS485_D2 I O 5V 4 NC 5 NC 6 NC 7 NC 8 NC 5V 12V PWR 5V 12V 9 GND GND RS 422 Mode Pin Pin Name Signal Type Signal Level 1 RS422_TX2 OUT 5V 2 NC 3 RS422_TX2 OUT 5V 4 NC 5 RS422_RX2 IN 6 NC 7 RS422_RX2 IN 8 NC 5V 12V PWR 5V 12V 9 GND GND ...

Page 45: ...an be set by BIOS Default is Digital I O Note 2 5V input max current 0 5A LPT Mode Pin Pin Name Signal Type Signal Level 1 STROBE IN 2 AFD I O 3 PD0 I O 4 ERROR IN 5 PD1 I O 6 PRINT I O 7 PD2 I O 8 SLIN I O 9 PD3 I O 10 GND GND 11 PD4 I O 12 GND GND 13 PD5 I O STROBE AFD ERROR PRINT SLIN GND GND GND GND GND GND GND GND 5V D0 D1 D2 D3 D4 D5 D6 D7 ACK BUSY PE SLCT ...

Page 46: ...Pin Name Signal Type Signal Level 14 GND GND 15 PD6 I O 16 GND GND 17 PD7 I O 18 GND GND 19 ACK IN 20 GND GND 21 BUSY IN 22 GND GND 23 PE IN 24 GND GND 25 SLCT IN 26 5V PWR 5V Digital I O Mode Note 5V input max current 0 5A Pin Pin Name Signal Type Signal Level 1 NC 2 NC ...

Page 47: ...Signal Type Signal Level 3 DIO0 I O 5V 4 NC 5 DIO1 I O 5V 6 NC 7 DIO2 I O 5V 8 NC 9 DIO3 I O 5V 10 GND GND 11 DIO4 I O 5V 12 GND GND 13 DIO5 I O 5V 14 GND GND 15 DIO6 I O 5V 16 GND GND 17 DIO7 I O 5V 18 GND GND 19 NC 20 GND GND 21 NC 22 GND GND 23 NC 24 GND GND 25 NC 26 5V PWR 5V ...

Page 48: ...ame Signal Type Signal Level 1 LAD0 I O 3 3V 2 LAD1 I O 3 3V 3 LAD2 I O 3 3V 4 LAD3 I O 3 3V 5 3 3V PWR 3 3V 6 LFRAME IN 7 LRESET OUT 3 3V 8 GND GND 9 LCLK OUT 10 I2C_CLK OUT 3 3V 11 I2C_DATA I O 3 3V 12 SERIRQ I O 3 3V LAD0 1 12 LAD1 LAD2 LAD3 LFRAME LRESET I2C_CLK I2C_DATA SERIRQ GND LCLK 3 3V ...

Page 49: ...12V can be set by JP4 Max current in power supply mode is 0 5A Note 2 COM2 RS 232 422 485 can be set by BIOS setting Default is RS 232 RS 232 Mode Pin Pin Name Signal Type Signal Level 1 DCD3 IN 2 DSR3 IN 3 RX3 IN 4 RTS3 OUT 5V 5 TX3 OUT 5V 6 CTS3 IN 7 DTR3 OUT 5V 8 RI3 5V 12V IN 5V 12V 9 GND GND 1 2 3 4 5 6 7 8 9 ...

Page 50: ...me Signal Type Signal Level 1 RS485_ D3 I O 5V 2 NC 3 RS485_D3 I O 5V 4 NC 5 NC 6 NC 7 NC 8 NC 5V 12V PWR 5V 12V 9 GND GND RS 422 Mode Pin Pin Name Signal Type Signal Level 1 RS422_TX3 OUT 5V 2 NC 3 RS422_TX3 OUT 5V 4 NC 5 RS422_RX3 IN 6 NC 7 RS422_RX3 IN 8 NC 5V 12V PWR 5V 12V 9 GND GND ...

Page 51: ...7 3 5 Subcompact Board GENE APL5 2 4 13 BIOS Debug Port CN13 Pin Pin Name Signal Type Signal Level 1 SPI_MISO OUT 2 GND GND 3 SPI_CLK IN 4 3 3VSB PWR 3 3V 5 SPI_MOSI IN 6 SPI_CS IN 7 NC P IN 1 P IN 2 P IN 3 P IN 4 P IN 5 P IN 6 P IN 7 ...

Page 52: ...on 38 3 5 Subcompact Board GENE APL5 2 4 14 COM Port 4 CN14 Pin Pin Name Signal Type Signal Level 1 DCD4 IN 2 DSR4 IN 3 RX4 IN 4 RTS4 OUT 9V 5 TX4 OUT 9V 6 CTS4 IN 7 DTR4 OUT 9V 8 RI4 IN 9 GND GND DCD DSR RX RTS TX CTS DTR RI GND ...

Page 53: ...ame Signal Type Signal Level 1 KB_ DATA I O 5V 2 KB_CLK I O 5V 3 GND GND 4 5VSB PWR 5V 5 MS_DATA I O 5V 6 MS_CLK I O 5V 2 4 16 USB 2 0 Port 2 CN16 Pin Pin Name Signal Type Signal Level 1 5VSB PWR 5V 2 USB_D DIFF 3 USB_D DIFF 4 GND GND 5 GND GND KB_CLK KB_DATA 1 4 6 2 MS_DATA 5VSB GND MS_CLK 5VSB USB_ D USB_ D GND GND ...

Page 54: ...t 3 CN17 Pin Pin Name Signal Type Signal Level 1 5VSB PWR 5V 2 USB_D DIFF 3 USB_D DIFF 4 GND GND 5 GND GND 2 4 18 COM Port 1 CN18 Wafer Optional Pin Pin Name Signal Type Signal Level 1 DCD1 IN 2 DSR1 IN 3 RX1 IN 4 RTS1 OUT 9V 5VSB USB_ D USB_ D GND GND DCD DSR RX RTS TX CTS DTR RI GND ...

Page 55: ... GENE APL5 Pin Pin Name Signal Type Signal Level 5 TX1 OUT 9V 6 CTS1 IN 7 DTR1 OUT 9V 8 RI1 IN 9 GND GND 2 4 19 USB 2 0 Port 4 CN19 Pin Pin Name Signal Type Signal Level 1 5VSB PWR 5V 2 USB_D DIFF 3 USB_D DIFF 4 GND GND 5 GND GND 5VSB USB_ D USB_ D GND GND ...

Page 56: ...e Signal Type Signal Level 1 5VSB PWR 5V 2 USB_D DIFF 3 USB_D DIFF 4 GND GND 5 GND GND 2 4 21 LVDS Port 2 CN21 Note LVDS2 LCD_PWR can be set to 3 3V or 5V by JP7 Max current is 2A Pin Pin Name Signal Type Signal Level 1 BKL_ENABLE OUT 2 BKL_CONTROL OUT 5VSB USB_ D USB_ D GND GND PIN 1 PIN 2 PIN 30 PIN 29 ...

Page 57: ...LCD_PWR PWR 3 3V 5V 8 GND GND 9 LVDS_DA0 DIFF 10 LVDS_DA0 DIFF 11 LVDS_DA1 DIFF 12 LVDS_DA1 DIFF 13 LVDS_DA2 DIFF 14 LVDS_DA2 DIFF 15 LVDS_DA3 DIFF 16 LVDS_DA3 DIFF 17 DDC_DATA I O 3 3V 18 DDC_CLK I O 3 3V 19 LVDS_DB0 DIFF 20 LVDS_DB0 DIFF 21 LVDS_DB1 DIFF 22 LVDS_DB1 DIFF 23 LVDS_DB2 DIFF 24 LVDS_DB2 DIFF 25 LVDS_DB3 DIFF 26 LVDS_DB3 DIFF 27 LCD_PWR PWR 3 3V 5V 28 GND GND ...

Page 58: ...e Pin Pin Name Signal Type Signal Level 1 GND GND 2 TOP EXCITE IN 3 BOTTOM EXCITE IN 4 LEFT EXCITE IN 5 RIGHT EXCITE IN 6 TOP SENSE IN 7 BOTTOM SENSE IN 8 LEFT SENSE IN 9 RIGHT SENSE IN GND 1 9 1 9 TOP EXCITE BOTTOM EXCITE LEFT EXCITE RIGHT EXCITE TOP SENSE BOTTOM SENSE LEFT SENSE RIGHT SENSE GND TOP BOTTOM LEFT RIGHT NC NC NC NC GND UL Y UR H LL L LR X SENSE NC NC NC 8 Wires 4 Wires ...

Page 59: ...Name Signal Type Signal Level 1 GND GND 2 TOP IN 3 BOTTOM IN 4 LEFT IN 5 RIGHT IN 6 NC 7 NC 8 NC 9 NC 5 Wire Mode Pin Pin Name Signal Type Signal Level 1 GND GND 2 UL Y IN 1 9 1 9 1 9 GND TOP BOTTOM LEFT RIGHT NC NC NC NC GND UL Y UR H LL L LR X SENSE S NC NC NC 8 Wires 4 Wires 5 Wires ...

Page 60: ... Board GENE APL5 Pin Pin Name Signal Type Signal Level 3 UR H IN 4 LL L IN 5 LR X IN 6 SENSE S IN 7 NC 8 NC 9 NC 2 4 23 CPU Fan CN23 Optional Pin Pin Name Signal Type Signal Level 1 GND GND 2 FAN_POWER PWR 12V 3 FAN_TAC IN GND 1 2 3 FAN_POWER FAN_TAC ...

Page 61: ...BKL_CONTROL OUT 3 GND GND 4 GND GND 5 BKL_ENABLE OUT 5V Note 1 LVDS2 BKL_PWR can be set to 5V or 12V by JP7 Note 2 LVDS2 BKL_CONTROL can be set by JP8 2 4 25 USB 3 0 Ports 0 and 1 CN25 Pin Pin Name Signal Type Signal Level 1 5VSB PWR 5V 2 USB_D DIFF 3 USB_D DIFF 4 GND GND BLK_PWR 2 3 4 5 1 BKL_CONTROL GND GND BKL_ENABLE 10 Port 1 Port 0 11 12 13 1 2 3 4 14 15 16 17 18 5 6 7 8 9 ...

Page 62: ...SSRX DIFF 7 GND GND 8 USB_SSTX DIFF 9 USB_SSTX DIFF 10 5VSB PWR 5V 11 USB_D DIFF 12 USB_D DIFF 13 GND GND 14 USB_SSRX DIFF 15 USB_SSRX DIFF 16 GND GND 17 USB_SSTX DIFF 18 USB_SSTX DIFF 2 4 26 LAN RJ 45 Port 2 CN26 Pin Pin Name Signal Type Signal Level 1 MDI0 DIFF 2 MDI0 DIFF 3 MDI1 DIFF 4 MDI2 DIFF 1 ACT LINK LED SPEED LED 8 ...

Page 63: ...Pin Name Signal Type Signal Level 5 MDI2 DIFF 6 MDI1 DIFF 7 MDI3 DIFF 8 MDI3 DIFF 2 4 27 LAN RJ 45 Port 1 CN27 Pin Pin Name Signal Type Signal Level 1 MDI0 DIFF 2 MDI0 DIFF 3 MDI1 DIFF 4 MDI2 DIFF 5 MDI2 DIFF 6 MDI1 DIFF 7 MDI3 DIFF 8 MDI3 DIFF 1 ACT LINK LED SPEED LED 8 ...

Page 64: ...SUB 9 Pin Pin Name Signal Type Signal Level 1 DCD IN 2 RX IN 3 TX OUT 9V 4 DTR OUT 9V 5 GND GND 6 DSR IN 7 RTS OUT 9V 8 CTS IN 9 RI IN 2 4 29 HDMI Port CN29 Optional Pin Pin Name Signal Type Signal Level 1 TMDS_DAT2 DIFF 2 GND GND 3 TMDS_DAT2 DIFF 4 TMDS_DAT1 DIFF 5 GND GND 1 5 6 9 1 2 18 19 ...

Page 65: ...ignal Level 6 TMDS_DAT1 DIFF 7 TMDS_DAT0 DIFF 8 GND GND 9 TMDS_DAT0 DIFF 10 TMDS_CLK DIFF 11 GND GND 12 TMDS_CLK DIFF 13 NC 14 NC 15 DDC_CLK I O 5V 16 DDC_DATA I O 5V 17 GND GND 18 5V I O 5V 19 HPLG_DETECT IN 2 4 30 Battery CN30 Pin Pin Name Signal Type Signal Level 1 3 3V PWR 3 3V 2 GND GND ...

Page 66: ... 2 4 31 VGA Port CN31 Pin Pin Name Signal Type Signal Level 1 RED OUT 2 GREEN OUT 3 BLUE OUT 4 NC 5 GND GND 6 RED_GND_RTN GND 7 GREEN_GND_RTN GND 8 BLUE_GND_RTN GND 9 5V PWR 5V 10 NC 11 NC 12 DDC_DATA I O 5V 13 HSYNC OUT 14 VSYNC OUT 15 DDC_CLK I O 5V 1 6 10 11 15 5 ...

Page 67: ... CN32 Pin Pin Name Signal Type Signal Level 1 UIM_PWR PWR 2 UIM_RST IN 3 UIM_CLK IN 4 NC 5 GND GND 6 UIM_VPP PWR 7 UIM_DATA I O 8 NC 2 4 33 Mini Card Slot Half Mini CN33 Pin Pin Name Signal Type Signal Level 1 PCIE_WAKE IN 2 3 3VSB PWR 3 3V 3 NC 4 GND GND 5 NC 6 1 5V PWR 1 5V 7 PCIE_CLK_REQ IN ...

Page 68: ...1 PCIE_REF_CLK DIFF 12 UIM_CLK IN 13 PCIE_REF_CLK DIFF 14 UIM_RST IN 15 GND GND 16 UIM_VPP PWR 17 NC 18 GND GND 19 NC 20 W_DISABLE OUT 3 3V 21 GND GND 22 PCIE_RST OUT 3 3V 23 PCIE_RX DIFF 24 3 3VSB PWR 3 3V 25 PCIE_RX DIFF 26 GND GND 27 GND GND 28 1 5V PWR 1 5V 29 GND GND 30 SMB_CLK I O 3 3V 31 PCIE_TX DIFF 32 SMB_DATA I O 3 3V 33 PCIE_TX DIFF ...

Page 69: ...6 USB_D DIFF 37 GND GND 38 USB_D DIFF 39 3 3VSB PWR 3 3V 40 GND GND 41 3 3VSB PWR 3 3V 42 NC 43 GND GND 44 NC 45 NC 46 NC 47 NC 48 1 5V PWR 1 5V 49 NC 50 GND GND 51 NC 52 3 3VSB PWR 3 3V 2 4 34 mSATA Full Size CN34 Note CN34 can be changed to Mini Card by BOM change Pin Pin Name Signal Type Signal Level 1 NC IN 2 3 3V PWR 3 3V ...

Page 70: ...Name Signal Type Signal Level 3 NC 4 GND GND 5 NC 6 1 5V PWR 1 5V 7 NC 8 NC 9 GND GND 10 NC 11 NC 12 NC 13 NC 14 NC 15 GND GND 16 NC 17 NC 18 GND GND 19 NC GND 20 NC 21 GND GND 22 NC OUT 23 SATA_RX DIFF 24 3 3V PWR 3 3V 25 SATA_RX DIFF 26 GND GND 27 GND GND 28 1 5V PWR 1 5V ...

Page 71: ...ype Signal Level 29 GND GND 30 SMB_CLK I O 3 3V 31 SATA_TX DIFF 32 SMB_DATA I O 3 3V 33 SATA_TX DIFF 34 GND GND 35 GND GND 36 NC 37 GND GND 38 NC 39 3 3V PWR 3 3V 40 GND GND 41 3 3V PWR 3 3V 42 NC 43 GND GND 44 NC 45 NC 46 NC 47 NC 48 1 5V PWR 1 5V 49 NC 50 GND GND 51 NC 52 3 3V PWR 3 3V ...

Page 72: ...3 5 Subcompact Board GENE APL5 Chapter 3 Chapter 3 AMI BIOS Setup ...

Page 73: ...gainst the values stored in the CMOS memory and BIOS NVRAM If a system configuration is not found or an error is detected the module will load the default configuration and reboot automatically There are four situations in which you will need to setup system configuration 1 You are starting your system for the first time 2 You have changed the hardware attached to your system 3 The system configur...

Page 74: ... Setup information when the power is turned off Entering Setup Power on the computer and press Del or ESC immediately This will allow you to enter Setup Main Date and time can be set here Press Tab to switch between date elements Advanced Access advanced hardware settings and options Chipset Chipset Host Bridge settings and options Security Set setup administrator password Boot Boot options includ...

Page 75: ...Chapter 3 AMI BIOS Setup 61 3 5 Subcompact Board GENE APL5 3 3 Setup Submenu Main ...

Page 76: ...Chapter 3 AMI BIOS Setup 62 3 5 Subcompact Board GENE APL5 3 4 Setup Submenu Advanced ...

Page 77: ...ce TCG EFI protocol and INT1A interface will not be available SHA 1 PCR Bank Disable Enable Optimal Default Failsafe Default Enable or Disable SHA 1 PCR Bank SHA256 PCR Bank Disable Enable Optimal Default Failsafe Default Enable or Disable SHA256 PCR Bank Pending Operation None Optimal Default Failsafe Default TPM Clear Schedule an Operation for the Security Device NOTE Your Computer will reboot d...

Page 78: ...ent Hierarchy Disabled Enabled Optimal Default Failsafe Default Enable or Disable Endorsement Hierarchy TPM2 0 UEFI Spec Version TCG_1_2 TCG_2 Optimal Default Failsafe Default Select the TCG2 Spec Version Support TCG_1_2 the Compatible mode for Win8 Win10 TCG_2 Support new TCG2 protocol and event format for Win10 or later Physical Presence Spec Version 1 2 1 3 Optimal Default Failsafe Default Sele...

Page 79: ...Default Failsafe Default Enable Disable C States EIST Disabled Enabled Optimal Default Failsafe Default Enable Disable Intel SpeedStep Turbo Mode Disabled Enabled Optimal Default Failsafe Default Turbo Mode Power Limit 1 Enable Disabled Optimal Default Failsafe Default Enabled Enable Disable Power Limit 1 Table Continues on Next Page ...

Page 80: ...ummary Intel Virtualization Technology Disabled Enabled Optimal Default Failsafe Default When enabled a VMM can utilize the additional hardware capabilities provided by Vanderpool Technology VT d Disabled Optimal Default Failsafe Default Enabled Enable Disable CPU VT d ...

Page 81: ...oller The Chipset SATA controller supports the 2 black internal SATA ports up to 3Gb s supported per port SATA GEN SPEED Auto Optimal Default Failsafe Default GEN1 GEN2 GEN3 SATA Gen Speed Selection Port 0 mSATA Disabled Enabled Optimal Default Failsafe Default Enables or Disables SATA Port SATA Port 0 Hot Plug Capability Disabled Optimal Default Failsafe Default Enabled Enables or Disables SATA h...

Page 82: ...Chapter 3 AMI BIOS Setup 68 3 5 Subcompact Board GENE APL5 3 4 3 1 PCI Express Configuration ...

Page 83: ...mmary PCIE Slot CN33 Disabled Enabled Optimal Default Failsafe Default Control PCIE Slot CN33 Hot Plug Disabled Optimal Default Failsafe Default Enabled PCIE Express Hot Plug Enable Disable PCIe Speed Auto Optimal Default Failsafe Default Gen 1 Gen 2 Configure PCIe Speed ...

Page 84: ...Chapter 3 AMI BIOS Setup 70 3 5 Subcompact Board GENE APL5 3 4 4 Hardware Monitor Options Summary Smart Fan Disable Enable Optimal Default Failsafe Default Enables or Disables Smart Fan ...

Page 85: ...Duty Mode Auto Duty Cycle Mode Optimal Default Failsafe Default Smart Fan Mode Select Temperature Source CPU external Optimal Default Failsafe Default System Select the monitored temperature source for this fan Duty Cycle 1 85 Temperature 1 60 Auto fan speed control Fan speed will follow different temperature by different duty cycle 1 100 ...

Page 86: ...Chapter 3 AMI BIOS Setup 72 3 5 Subcompact Board GENE APL5 3 4 5 SIO Configuration ...

Page 87: ...se This Device Disable Enable Optimal Default Failsafe Default Enable or Disable this Logical Device Possible Use Automatic Settings Optimal Default Failsafe Default IO 3F8h IRQ 4 IO 2F8h IRQ 3 Allows user to change Device s Resource settings New settings will be reflected on This Setup Page after System restarts ...

Page 88: ...lt Failsafe Default Enable or Disable this Logical Device Possible Use Automatic Settings Optimal Default Failsafe Default IO 2F8h IRQ 3 IO 3F8h IRQ 4 Allows user to change Device s Resource settings New settings will be reflected on This Setup Page after System restarts Mode RS232 Optimal Default Failsafe Default RS422 RS485 UART RS232 422 485 selection ...

Page 89: ...t Failsafe Default Enable or Disable this Logical Device Possible Use Automatic Settings Optimal Default Failsafe Default IO 3E8h IRQ 11 IO 2E8h IRQ 11 Allows user to change Device s Resource settings New settings will be reflected on This Setup Page after System restarts Mode RS232 Optimal Default Failsafe Default RS422 RS485 UART RS232 422 485 selection ...

Page 90: ...e This Device Disable Enable Optimal Default Failsafe Default Enable or Disable this Logical Device Possible Use Automatic Settings Optimal Default Failsafe Default IO 2E8h IRQ 10 IO 3E8h IRQ 10 Allows user to change Device s Resource settings New settings will be reflected on This Setup Page after System restarts ...

Page 91: ...er 3 AMI BIOS Setup 77 3 5 Subcompact Board GENE APL5 3 4 5 5 Parallel Port Configuration Options Summary Use This Device Disable Enable Optimal Default Failsafe Default Enable or Disable this Logical Device ...

Page 92: ...ault AT Type Select system power mode Power Saving ERP Control Disabled Optimal Default Failsafe Default Enabled Configure power mode for power saving function Restore AC Power Loss Last State Optimal Default Failsafe Default Always On Always Off RTC wake system from S5 Disable Optimal Default Failsafe Default Fixed Time Select system power mode ...

Page 93: ...9 3 5 Subcompact Board GENE APL5 3 4 7 Digital IO Port Configuration Options Summary DIO Port Output Input Set DIO as Input or Output Output Level High Optimal Default Failsafe Default Low Set output level when DIO pin is output ...

Page 94: ...Chapter 3 AMI BIOS Setup 80 3 5 Subcompact Board GENE APL5 3 5 Setup Submenu Chipset ...

Page 95: ...Chapter 3 AMI BIOS Setup 81 3 5 Subcompact Board GENE APL5 3 5 1 North Bridge ...

Page 96: ... two LVDS ports Options Summary LVDS Disabled Enabled Optimal Default Failsafe Default Enable Disabled this panel LVDS Panel Type 640x480 60Hz 800x480 60Hz 800x600 60Hz 1024x600 60Hz 1024x768 60Hz Optimal Default Failsafe Default 1280x768 60Hz 1280x800 60Hz 1280x1024 60Hz 1366x768 60Hz 1440x900 60Hz 1600x1200 60Hz 1920x1080 60Hz 1920x1200 60Hz ...

Page 97: ...fe Default 24 bit 36 bit 48 bit Select panel type Backlight Type Normal Optimal Default Failsafe Default Inverted Select backlight control signal type Backlight Level 0 10 20 30 40 50 60 70 80 Optimal Default Failsafe Default 90 100 Select backlight control level Backlight PWM Freq 100Hz 200Hz 220Hz Optimal Default Failsafe Default 500Hz 1KHz 2 2KHz 6 5KHz Select PWM frequency of backlight control...

Page 98: ...hen the user enters the Setup utility A User Password does not provide access to many of the features in the Setup utility Select the password you wish to set and press Enter In the dialog box enter your password must be between 3 and 20 letters or numbers Press Enter and retype your password to confirm Press Enter again to set the password Removing the Password Select the password you want to rem...

Page 99: ...em is in User mode The mode change requires platform reset Secure Boot Mode Custom Optimal Default Failsafe Default Standard Secure Boot mode options Standard or Custom In Custom mode Secure Boot Policy variables can be configured by a physically present user without full authentication Restore Factory Keys Force System to User Mode Install factory default Secure Boot key databases Reset To Setup ...

Page 100: ...de change requires platform reset Restore Factory Keys Force System to User Mode Install factory default Secure Boot key databases Reset To Setup Mode Delete all Secure Boot key databases from NVRAM Export Secure Boot variables Copy NVRAM content of Secure Boot variables to files in a root folder on a file system device Enroll Efi Image Allow the image to run in Secure Boot mode Enroll SHA256 Hash...

Page 101: ...Delete Key Exchange Keys Details Export Update Append Delete Authorized Signatures Details Export Update Append Delete Forbidden Signatures Details Export Update Append Delete Authorized Time Stamps Update Append OsRecovery Signatures Update Append Enroll Factory Defaults or load certificates from a file 1 Public Key Certificate a EFI_SIGNATURE_LIST b EFI_CERT_X509 DER c EFI_CERT_RSA2048 bin d EFI...

Page 102: ...owing boot logo Monitor Mwait Disable Enabled Auto Optimal Default Failsafe Default Enable Disable Monitor Mwait To install Linux OS please set this item to disable Ipv4 PXE Support Disabled Optimal Default Failsafe Default Enabled Enable Ipv4 PXE Boot Support If disabled IPV4 PXE boot option will not be created Note When installing Linux OS set the Monitor Mwait to Disabled ...

Page 103: ...Chapter 3 AMI BIOS Setup 89 3 5 Subcompact Board GENE APL5 3 8 Setup Submenu Save Exit ...

Page 104: ...Chapter 3 AMI BIOS Setup 90 3 5 Subcompact Board GENE APL5 3 9 User Notes When installing Linux OS set the Monitor Mwait to Disabled See Ch 3 7 Boot ...

Page 105: ...3 5 Subcompact Board GENE APL5 Chapter 4 Chapter 4 Drivers Installation ...

Page 106: ... the steps below to install them Step 1 Install Chipset Drivers 1 Open the Step1 Chipset folder followed by SetupChipset exe 2 Follow the instructions 3 Drivers will be installed automatically Step 2 Install Graphics Drivers 1 Open the Step2 VGA folder followed by Setup exe 2 Follow the instructions 3 Drivers will be installed automatically Step 3 Install LAN Drivers 1 Click on the Step3 LAN folde...

Page 107: ...tep 5 Install TXE Driver 1 Open the Step5 TXE folder followed by SetupTXE exe 2 Follow the instructions 3 Drivers will be installed automatically Step 6 Install Touch Driver 1 Open the Step6 Touch folder followed by Setup exe 2 Follow the instructions 3 Drivers will be installed automatically Step 7 Install GPIO Driver 1 Open the Step6 GPIO folder followed by SetupSerialIO exe 2 Follow the instruc...

Page 108: ...3 5 Subcompact Board GENE APL5 Appendix A Appendix A I O Information ...

Page 109: ...Appendix A I O Information 95 3 5 Subcompact Board GENE APL5 A 1 I O Address Map ...

Page 110: ...Appendix A I O Information 96 3 5 Subcompact Board GENE APL5 ...

Page 111: ...Appendix A I O Information 97 3 5 Subcompact Board GENE APL5 A 2 Memory Address Map ...

Page 112: ...Appendix A I O Information 98 3 5 Subcompact Board GENE APL5 A 3 IRQ Mapping Chart ...

Page 113: ...Appendix A I O Information 99 3 5 Subcompact Board GENE APL5 ...

Page 114: ...Appendix A I O Information 100 3 5 Subcompact Board GENE APL5 ...

Page 115: ...Appendix A I O Information 101 3 5 Subcompact Board GENE APL5 ...

Page 116: ...Appendix A I O Information 102 3 5 Subcompact Board GENE APL5 ...

Page 117: ...3 5 Subcompact Board GENE APL5 Appendix B Appendix B Mating Connectors ...

Page 118: ...6 N A N A CN2 LVDS Port1 Inverter Connector JST PHR 5 N A N A CN3 5Vout Connector JST PHR 2 2 Pins for SATA HDD Power 1702150155 CN4 SATA Connector Molex 887505318 SATA Cable 1709070500 CN5 Power Input Connector Molex 19211 0003 Power Cable 170204010R CN6 External 5VSB Power Input and PS_ON JST XHP 3 ATX Cable 170220020B CN7 Audio Connector Molex 51021 1000 Audio Cable 1709100254 CN8 LVDS Port1 Co...

Page 119: ... Cable 1701090150 CN14 COM Port 4 Connector Molex 51021 0900 Serial Port Cable 1701090150 CN15 PS 2 KB MS Connector JST PHDR 06VS PS 2 KB MS Cable 1700060152 CN16 USB Port 2 Connector Molex 51021 0500 USB Cable 1700050207 CN17 USB Port 3 Connector Molex 51021 0500 USB Cable 1700050207 CN19 USB Port 4 Connector Molex 51021 0500 USB Cable 1700050207 CN20 USB Port 5 Connector Molex 51021 0500 USB Cab...

Page 120: ...Ports 106 3 5 Subcompact Board GENE APL5 Connector Label Function Mating Connector Available Cable Cable P N Vendor Model No CN24 LVDS Port1 Inverter Connector JST PHR 5 N A N A CN30 External RTC Connector Molex 51021 0200 Battery Cable 175011301C ...

Page 121: ...3 5 Subcompact Board GENE APL5 Appendix C Appendix C Electrical Specifications for I O Ports ...

Page 122: ... 12V 5V 1A or 12V 1A COM Port 2 CN10 5V 5V 1A Digital IO Port CN12 5V 12V 5V 1A or 12V 1A COM Port 3 CN16 5VSB 5V 0 5A USB 2 0 Ports 2 CN17 5VSB 5V 0 5A USB 2 0 Ports 3 CN19 5VSB 5V 0 5A USB 2 0 Ports 4 CN20 5VSB 5V 0 5A USB 2 0 Ports 5 CN21 3 3V 5V 3 3V 2A or 5V 2A LVDS Port2 CN23 12V 12V 0 5A CPU FAN CN24 5V 12V 5V 1 5A or 12V 1 5A LVDS Port2 Inverter Backlight Connector CN25 5VSB 5V 1A per chan...

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