Aaeon FWS-8500, User Manual, Page: 52 / 74

Chapter 3 – AMI BIOS Setup 40
Net
work
Ap
plian
ce
FW
S-
8500
Data Bits
7
8 Optimal Default, Failsafe Default
Data Bits
Parity
None Optimal Default, Failsafe Default
Even
Odd
Mark
Space
A parity bit can be sent with the data bits to detect some transmission errors. Even:
parity bit is 0 if the num of 1’s in the data bits is even. Odd: parity bit is 0 if num of 1’s in
the data bits is odd. Mark: parity bit is always 1. Space: Parity bit is always 0. Mark and
Space Parity do not allow for error detection.
Stop Bits
1 Optimal Default, Failsafe Default
2
Stop bits indicate the end of a serial data packet. ( A start bit indicates the beginning).
The standard setting is 1 stop bit. Communication with slow devices may require more
than 1 stop bit.
Flow Control
None Optimal Default, Failsafe Default
Hardware RTC/CTS
Flow control can prevent data loss from buffer overflow. When sending data, if the
receiving buffers are full, a ‘stop’ signal can be sent to stop the data flow. Once the
buffers are empty, a ‘start’ signal can be sent to re-start the flow. Hardware flow control
uses two wires to send start/stop signals.
VT-UTF8 Combo Key Sup
Enable Optimal Default, Failsafe Default
Disable
Enable VT-UTF8 Combination Key Support for ANSI/VT100 terminals
Recorder Mode
Enable
Disable Optimal Default, Failsafe Default
With this mode enabled only text will be send. This is to capture Terminal data.
Resolution 100x31
Enable
Disable Optimal Default, Failsafe Default
Enables or disables extended terminal resolution
Legacy OS Redirection
80x24 Optimal Default, Failsafe Default
80x24
On Legacy OS, the Number of Rows and Columns supported redirection
Putty KeyPad
VT100 Optimal Default, Failsafe Default
LINUX
XRERMR6
SCO
ESCN