C a r r i e r B o a r d
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Quick Installation Guide
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When this signals is asserted, a PCI cycle is started.
DEVSEL#
Device select signal. When the target device has decoded
the address as its own cycle, it will assert DEVSEL#
TRDY#
Target ready signal. When a device is ready to complete
data transaction, it asserts this signal.
IRDY#
Initial ready signals. A PCI initiator assert this signal when it
is ready to complete data transaction.
STOP#
The signal is asserted by target to request initiator to stop
the current PCI transaction.
PCICLK1 – PCICLK4
PCI clock signals for each PCI slots.
REQ0# - REQ3# (PREQ#0-PREQ#3)
PCI bus request signals for each PCI slots. A PCI device
assert this signal to gain the control of PCI bus from host
bridge.
GNT0# - GNT3# (PGNT#0-PGNT#3)
PCI bus grant signals for each PCI slots. Host Bridge asserts
this signal to a PCI device and allows it to be a PCI master.
INTA#, INTB#,INTC#,INTD# (INT#A, INT#B,INT#C,INT#D)
PCI interrupt request signals. Rout all four signals to each
PCI slots.
