S M AR C M o d u l e
μ C O M - B T
Auto
Configuration
Disable
Optimal Default, Failsafe Default
Enables or Disables BIOS ACPI Auto Configuration
Enable
Hibernation
Enable
Optimal Default, Failsafe Default
Disable
Enables or Disables System ability to Hibernate (OS/S4 Sleep State). This
option may be not effective with some OS
ACPI Sleep State Suspend Disabled
Optimal Default, Failsafe Default
S3 only(Suspend to
RAM)
Select highest ACPI sleep state the System will enter when the Suspend
button is pressed
Lock Legacy
Resources
Enable
Optimal Default, Failsafe Default
Disable
Enables or Disables Lock of Legacy Resources
Wake on LAN
Enable
Optimal Default, Failsafe Default
Disable
Enabled/Disabled wake from LAN
S5 RTC Wake
Settings
Enable system to wake from S5 using RTC alarm.
Chapter 3 AMI BIOS Setup
3-7
Summary of Contents for ?COM-BT
Page 9: ...SMARC Module μ C O M B T General Information Chapter 1 Chapter 1 General Information 1 1 ...
Page 19: ...SMARC Module μ C O M B T Chapter 2 Quick Installation Guide 2 5 Heat Sink ...
Page 20: ...SMARC Module μ C O M B T Chapter 2 Quick Installation Guide 2 6 Heat Spreader ...
Page 31: ...SMARC Module μ C O M B T AMI BIOS Setup Chapter 3 Chapter 3 AMI BIOS Setup 3 1 ...
Page 34: ...SMARC Module μ C O M B T Main Press Delete Key to enter Setup Chapter 3 AMI BIOS Setup 3 4 ...
Page 35: ...SMARC Module μ C O M B T Advanced Chapter 3 AMI BIOS Setup 3 5 ...
Page 47: ...SMARC Module μ C O M B T Other PCI devices UEFI Default Legacy Chapter 3 AMI BIOS Setup 3 17 ...
Page 53: ...SMARC Module μ C O M B T Chipset Chapter 3 AMI BIOS Setup 3 23 ...
Page 55: ...SMARC Module μ C O M B T Chipset Host Bridge IGD LCD Control Chapter 3 AMI BIOS Setup 3 25 ...
Page 56: ...SMARC Module μ C O M B T Chipset South Bridge Chapter 3 AMI BIOS Setup 3 26 ...
Page 66: ...SMARC Module μ C O M B T Exit Chapter 3 AMI BIOS Setup 3 36 ...
Page 67: ...SMARC Module μ C O M B T Driver Installation Chapter 4 Chapter 4 Driver Installation 4 1 ...
Page 78: ...SMARC Module μ C O M B T I O Information Appendix B Appendix B I O Information B 1 ...
Page 79: ...SMARC Module μ C O M B T B 1 I O Address Map Appendix B I O Information B 2 ...
Page 80: ...SMARC Module μ C O M B T Appendix B I O Information B 3 ...
Page 81: ...SMARC Module μ C O M B T B 2 Memory Address Map Appendix B I O Information B 4 ...
Page 82: ...SMARC Module μ C O M B T B 3 IRQ Mapping Chart Appendix B I O Information B 5 ...
Page 83: ...SMARC Module μ C O M B T Appendix B I O Information B 6 ...
Page 84: ...SMARC Module μ C O M B T Appendix B I O Information B 7 ...
Page 85: ...SMARC Module μ C O M B T Appendix B I O Information B 8 ...
Page 86: ...SMARC Module μ C O M B T Appendix B I O Information B 9 ...
Page 87: ...SMARC Module μ C O M B T Appendix B I O Information B 10 ...
Page 88: ...SMARC Module μ C O M B T Appendix B I O Information B 11 ...
Page 89: ...SMARC Module μ C O M B T Appendix B I O Information B 12 ...
Page 90: ...SMARC Module μ C O M B T Appendix B I O Information B 13 ...
Page 91: ...SMARC Module μ C O M B T Appendix B I O Information B 14 ...
Page 92: ...SMARC Module μ C O M B T Appendix B I O Information B 15 ...
Page 93: ...SMARC Module μ C O M B T Appendix B I O Information B 16 ...
Page 100: ...SMARC Module μ C O M B T return hr Appendix D Electrical Specifications for I O Ports C 7 ...