Aaeon All-in-One Super7 Single Board Computer..., User Manual

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62 PCM-5896 User Manual
I/O Recovery Time
The I/O recovery mechanism adds bus clock cycles between PCI-
originated I/O cycles to the ISA bus. This delay takes place
because the PCI bus is so much faster than the ISA bus.
Passive Release
When Enabled, CPU to PCI bus accesses are allowed during
passive release. Otherwise, the arbiter only accepts another PCI
master access to local DRAM.
Delayed Transaction
The chipset has an embedded 32-bit posted write buffer to support
delay transactions cycles. Select Enabled to support compliance
with PCI specification version 2.1.
Auto Detect DIMM/PCI Clk
When the Auto Detect DIMM/PCI clk enable, the Utility will
automatically detect the DIMM/PCI clock in your system.
Spread Spectrum
When the system clock generator pulses, the extreme values of the
pulse generate excess EMI. Enabling pulse spectrum spread
modulation changes the extreme values from spikes to flat curves,
thus reducing EMI. This benefit may in some cases be outweighed
by problems with timing-critical devices, such as a clock-sensitive
SCSI device
IN0-IN6(V)
These fields display the current voltage of up to seven voltage
input lines, if your computer contains a monitoring system.