AAC Microtec Sirius User Manual Download

Page: 61 / 106

Document number

204911

Version

Rev. K

Issue date

2016-10-11

Sirius Breadboard User Manual

www.aacmicrotec.com

Page

106

5.10.2.2. Datatype struct tc_frame_t

This datatype is a struct representing a telecommand transfer frame. The elements are
described in the table below:

Element

Size (in bits)

Description

transfer_frame_version_no

The transfer frame version number

bypass_flag

The bypass flag

control_command_flag

The control command flag

Spare

Reserved for future use

Scid

The SCID

Vcid

The virtual channel id

frame_length

The TC frame length

data_field

1017*8

The data field of the TC frame

Crc

The CRC

5.10.2.3. Data type dma_descriptor_t

This datatype is a struct for DMA descriptors. The elements of the struct are described
below:

Element

Type

Description

desc_no

uint32_t

The descriptor number (0-31)

desc_config

uint32_t

The configuration of the DMA
descriptor

desc_adress

uint32_t

The configuration of the DMA address
descriptor

5.10.2.4. Data type tm_config_t

This datatype is a struct for configuration of the TM path. The elements of the struct are
described below:

Element

Type

Description

clk_divisor

uint8_t

The divisor of the clock

tm_enabled

uint8_t

Enable/disable of telemetry
0 - Disable
1 - Enable

fecf_enabled

uint8_t

Enable/disable of FECF
0 - Disable
1 - Enable

mc_cnt_enabled

uint8_t

Enable/Disable of master channel
frame counter
0 - Disable
1 - Enable

idle_frame_enabled

uint8_t

Enable/disable of generation of Idle
frames
0 - Disable
1 - Enable

ocf_clcw_enabled

uint8_t

Enable/disable of OCF/CLCW in TM
Transfer frames
0

– Disable

– Enable

Summary of Contents for Sirius

Page 1: ...adboard User Manual Rev K ÅAC Microtec 2016 ÅAC Microtec AB owns the copyright of this document which is supplied in confidence and which shall not be used for any purpose other than for which it is supplied and shall not in whole or in part be reproduced copied or communicated to any person without written permission from the owner ...

Page 2: ...hanges H 2016 06 30 Version H released with the following updates PUS 2 commands CDPU SoC specs TCM S core app updates SPW byte alignment I 2016 09 05 Version I released with the following updates GPIO example HK equations ADC section nandflash program bad blocks handling Boot image information and boot order Added section on pulse command inputs Adjusted TCM S section and synched with TCM S DDD R...

Page 3: ... Deploying a Sirius application 13 3 5 1 Establish a debugger connection to the Breadboard 13 3 5 2 Setup a serial terminal to the device debug UART 14 3 5 3 Loading the application 14 3 6 Programming an application boot image to system flash 15 4 SOFTWARE DEVELOPMENT 16 4 1 RTEMS step by step compilation 16 4 2 Software disclaimer of warranty 16 5 RTEMS 17 5 1 Introduction 17 5 2 Watchdog 18 5 2 ...

Page 4: ...8 5 10 CCSDS 59 5 10 1 Description 59 5 10 2 RTEMS API 59 5 10 3 Usage description 66 5 11 ADC 67 5 11 1 Description 67 5 11 2 RTEMS API 67 5 11 3 Usage 70 5 11 4 Limitations 71 5 12 NVRAM 71 5 12 1 Description 72 5 12 2 RTEMS API 72 5 12 3 Usage description 75 6 SPACEWIRE ROUTER 76 7 TCM STM 77 7 1 Description 77 7 2 Block diagram 77 7 3 Spacewire RMAP 78 7 3 1 Input 78 7 3 2 Output 79 7 4 RMAP a...

Page 5: ...S 2 Device Command Distribution Service 88 7 8 Limitations 88 8 SYSTEM ON CHIP DEFINITIONS 89 8 1 Memory mapping 89 8 2 Interrupt sources 90 8 3 SCET timestamp trigger sources 90 8 4 Boot images and boot procedure 91 8 4 1 Description 91 8 4 2 Block diagram 91 8 4 3 Usage description 91 8 4 4 Limitations 92 8 5 Reset behaviour 92 8 6 Pulse command inputs 92 8 7 SoC information map 92 9 CONNECTOR I...

Page 6: ...1 Sirius Breadboard User Manual www aacmicrotec com Page 6 of 106 10 UPDATING THE SIRIUS FPGA 103 10 1 Prerequisite hardware 103 10 2 Prerequisite software 103 10 3 Step by step guide 103 11 MECHANICAL DATA 104 12 ENVIRONMENTAL INFORMATION 104 13 GLOSSARY 105 ...

Page 7: ...ritten for the software engineers using the ÅAC Sirius product suite 1 3 Getting support If you encounter any problem using the breadboard or another ÅAC product please use the following address to get help Email support aacmicrotec com 1 4 Reference documents RD Document ref Document name RD1 http opencores org openrisc architecture OpenRISC 1000 Architecture Manual RD2 ECSS E ST 50 12C SpaceWire...

Page 8: ...B EDAC running 100MHz Spacecraft Elapsed Timer SCET for accurate time measurement with a resolution of 15 µs SpaceWire including a three port SpaceWire router for communication with external peripheral units UARTs Number of interfaces differ between the products uses the RS422 and RS485 line drivers on the board with line driver mode set by software GPIOs Watchdog fail safe mechanism to prevent a ...

Page 9: ...hat parts are not yet implemented since the products are still under development FPGA FPU OpenRISC 1200FT I D Cache I2C UART GPIO CCSDS Memory controller System flash controller Flash controller SpaceWire DMA Control Watchdog Debug Unit SCET Error manager 2x 64MB SDRAM 2 GB System Flash Radio Interfaces RS422 LVDS RS422 RS485 JTAG DEBUG Pulse CMD UMBI EGSE ETHERNET GPIO ADC Housekeeping Ethernet 1...

Page 10: ...t with super user rights USB 2 0 Recommended applications and software Installed terminal e g gtkterm or minicom Driver for USB COM port converter FTDI www ftdichip com Host build system e g debian package build essential The following software is installed by the ÅAC toolchain package o GCC C compiler for OpenRISC o GCC C compiler for OpenRISC o GNU binutils and linker for OpenRISC For FPGA updat...

Page 11: ...104451 ÅAC Debugger and Ethernet adapter with the 104471 Ethernet debug unit cable to connector 3 Connect the adapter USB connector to the host PC The ÅAC debugger is mainly used for development of custom software for the OBC S with monitoring debug capabilities but is also used for programming an image to the system flash memory For further information refer to chapter 3 6 For FPGA updating only ...

Page 12: ...r describes instructions for installing the aac or1k toolchain 3 3 1 Supported Operating Systems Debian 7 64 bit Debian 8 64 bit 3 3 2 Installation Steps 1 Add the ÅAC Package Archive Server Open a terminal and execute the following command sudo gedit etc apt sources list d aac repo list This will open a graphical editor add the following lines to the file and then save and close it deb http repo ...

Page 13: ...arball aac or1k xxx x bsp y tar bz2 to a directory of your choice xxx x depends on your intended hardware target OBC S or TCM s and y matches the current version number of that BSP The newly created directory aac or1k xxx x bsp now contains the drivers for both bare metal applications and RTEMS See the included README and chapter 4 1 for build instructions 3 5 Deploying a Sirius application 3 5 1 ...

Page 14: ...top bits 1 Parity None Hardware flow control Off On a clean system with no other USB to serial devices connected the serial port will appear as dev ttyUSB1 However the numbering may change when other USB devices are connected and you have to make sure you re using the correct device number to communicate to the board s debug UART 3 5 3 Loading the application Application loading during the develop...

Page 15: ...t image for this release is 16 Mbyte The nandflash_program application can be found in the BSP see also instructions below The below instructions assume that the toolchain is in the PATH see section 3 3 for how to accomplish this 1 Compile the boot image binary according to the rules for that program 2 Then make sure that this is in a binary only format and not ELF This can otherwise be accomplish...

Page 16: ...e 3 Once the build is complete the build target directory is librtems 4 Set the RTEMS_MAKEFILE_PATH environment variable to point to the librtems directory export RTEMS_MAKEFILE_PATH path to librtems or1k aac rtems4 11 or1k aac 5 Enter the example directory and build the test application by issuing cd example make Load the resulting application using the debugger according to the instructions in c...

Page 17: ...Breadboard User Manual www aacmicrotec com Page 17 of 106 5 RTEMS 5 1 Introduction This section presents the RTEMS drivers The Block diagram representing driver functionality access via the RTEMS API is shown in Figure 5 1 Figure 5 1 Functionality access via RTEMS API ...

Page 18: ...he device it can only be opened once at a time Argument name Type Direction Description filename char in The absolute path to the file that is to be opened Watchdog device is defined as RTEMS_WATCHDOG_DEVICE_NAME dev watchdog oflags int in A bitwise or separated list of values that determine the method in which the file is to be opened whether it should be read only read write Return value Descrip...

Page 19: ... the timeout Argument name Type Direction Description fd int in File descriptor received at open cmd int in Command to send val int in Data to write Command table Val interpretation WATCHDOG_ENABLE_IOCTL 1 Enables the watchdog 0 Disables the watchdog WATCHDOG_SET_TIMEOUT_IOCTL 0 255 Number of seconds until the watchdog barks Return value Description 0 Command executed successfully 1 see errno valu...

Page 20: ... closed when not needed Figure 5 2 RTEMS driver usage description Note All calls to the RTEMS driver are blocking calls 5 2 3 2 RTEMS application example In order to use the watchdog driver on the RTEMS environment the following code structure is suggested to be used Inclusion of fcntl h and unistd h are required for using the POSIX functions open close lseek read and write include bsp h include f...

Page 21: ...TEMS driver The driver functionality is accessed through the RTEMS POSIX API for ease of use In case of failure on a function call the errno value is set for determining the cause The error manager driver does not support writing nor reading to the device file Instead register accesses are performed using ioctls The driver exposes a message queue for receiving interrupt driven events such as power...

Page 22: ...s the running firmware ERRMAN_GET_SCRUBBER_IOCTL Gets the scrubber 1 On 0 Off ERRMAN_GET_RESET_ENABLE_IOCTL Gets the reset enable register ERRMAN_GET_WDT_ERRCNT_IOCTL Gets the watchdog error count register ERRMAN_GET_EDAC_SINGLE_ERRCNT_IOCTL Gets the EDAC single error count register ERRMAN_GET_EDAC_MULTI_ERRCNT_IOCTL Gets the EDAC multiple error count register ERRMAN_GET_CPU_PARITY_ERRCNT_IOCTL Ge...

Page 23: ...detected for system flash data Clear flag by write a 1 12 ERRMAN_SYS_SEFLG R W A previous EDAC Single Error Reset has been detected for system flash data Clear flag by write a 1 11 ERRMAN_PULSEFLG R W Pulse command flag bit is set Clear flag by write a 1 10 ERRMAN_POWFLG R W The power loss signal has been set 9 ERRMAN_MEMCLR R The memory cleared signal is set from the scrubber unit function from t...

Page 24: ... CF set 1 Counter overflow Cleared by write 1 4 ERRMAN_MECFLG R W Carry flag set when RAM EDAC Multiple Error counter overflow has occurred 0 No CF set 1 Counter overflow Cleared by write 1 3 ERRMAN_SECFLG R W Carry flag set when RAM EDAC Single Error counter overflow has occurred 0 No CF set 1 Counter overflow Cleared by write 1 2 ERRMAN_WDTCFLG R W Carry flag set when Watch Dog Timer counter ove...

Page 25: ... to The name of the queue is E M G R This queue emits messages upon power loss and single correctable errors A subscriber must inspect the message according to the following table to determine whether to take action or not Multiple subscribers are allowed and all subscribers will be notified upon a message Message Description ERRMAN_IRQ_POWER_LOSS A power loss has been detected ERRMAN_IRQ_EDAC_MUL...

Page 26: ... name RTEMS_ERROR_MANAGER_DEVICE_NAME CONFIGURE_APPLICATION_NEEDS_ERROR_MANAGER_DRIVER must be defined for using the error manager driver By defining this as part of RTEMS configuration the driver will automatically be initialised at boot up 5 3 4 Limitations Many of the error mechanisms are currently unverifiable outside of radiation testing due to the lack of mechanisms of injecting errors in th...

Page 27: ...orts a number of different IOCTLs Finally there is a message queue interface allowing the application to act upon different events 5 4 2 1 int open Opens access to the device it can only be opened once at a time Argument name Type Direction Description filename char in The absolute path to the file that is to be opened SCET device is defined as RTEMS_SCET_DEVICE_NAME oflags int in A bitwise or sep...

Page 28: ... the current interrupt status register SCET_GET_PPS_ARRIVE_COUNTER_IOCTL uint32_t out Returns the PPS arrived counter Bit 23 16 contains lower 8 bits of second Bit 15 0 contains fraction of second SCET_GET_GP_TRIGGER_COUNTER_IOCTL uint32_t in out Pointer input argument is the GP trigger Returns the counter of the selected GP trigger Bit 23 16 contains lower 8 bits of second Bit 15 0 contains fract...

Page 29: ...nd driver is to track the time since power on and to act as a source of timestamps By utilizing the GP triggers one can trap the timestamp of different events An interrupt trigger can optionally be set up to notify the CPU of that the GP trigger has fired If an external PPS source is used an interrupt trigger can be used to synchronize the SCET by reading out the SCET second and subsecond value at...

Page 30: ...ond count difference to adjust with The last 2 bytes contains the subsecond count difference to adjust with 2 Using the SCET_SET_SECONDS_IOCTL and SCET_SET_SUBSECONDS_IOCTL system calls defined in 5 4 2 3 Negative adjustment is done by writing data in two complement notations 5 4 3 1 2 Event callback via message queue The SCET driver exposes three message queues This queue is used to emit messages...

Page 31: ...ame Description TRIGGER1 Trigger 1 was triggered S G T 2 handles messages sent from the general purpose trigger 2 Event name Description TRIGGER2 Trigger 2 was triggered S G T 3 handles messages sent from the general purpose trigger 3 Event name Description TRIGGER3 Trigger 3 was triggered 5 4 3 2 Typical SCET use case A typical SCET use case scenario is to connect a GPS PPS pulse to the PPS input...

Page 32: ...ures Inclusion of bsp scet_rtems h is required for accessing scet device name RTEMS_SCET_DEVICE_NAME CONFIGURE_APPLICATION_NEEDS_SCET_DRIVER must be defined for using the scet driver By defining this as part of RTEMS configuration the driver will automatically be initialized at boot up include bsp h include fcntl h include unistd h include errno h include bsp scet_rtems h define CONFIGURE_APPLICAT...

Page 33: ...his has now been changed to instead mean 1 character 1 4 of the FIFO is full 1 2 of the FIFO is full and the FIFO is 2 characters from the given buffer depth top This results in the IP being fully backwards compatible since a buffer depth of 16 characters would yield the same trigger levels as those given in RD5 5 5 2 RTEMS API This API represents the driver interface of the module from an RTEMS u...

Page 34: ...5 only 5 5 2 2 Function int close Closes access to the device and disables the line drivers Argument name Type Direction Description fd int in File descriptor received at open Return value Description 0 Device closed successfully 5 5 2 3 Function ssize_t read Read data from the UART The call blocks until data is received from the UART RX FIFO Please note that it is not uncommon for the read call t...

Page 35: ...ters that were written 1 see errno values errno values EINVAL Invalid number of characters to be written 5 5 2 5 Function int ioctl Ioctl allows for toggling the RS422 RS485 Loopback mode and setting the baud rate RS422 RS485 mode selection is not applicable for safe bus and power ctrl UARTs Argument name Type Direction Description fd int in File descriptor received at open cmd int in Command to s...

Page 36: ...s UART_BUFFER_DEPTH_16 default UART_BUFFER_DEPTH_32 UART_BUFFER_DEPTH_64 UART_BUFFER_DEPTH_128 UART_IOCTL_GET_BUFFER_DEPTH uint32_t out Get the current buffer depth UART_IOCTL_SET_TRIGGER_LEVEL uint32_t in Set the RX FIFO trigger level Possible values UART_TRIGGER_LEVEL_1 1 character UART_TRIGGER_LEVEL_4 1 4 full UART_TRIGGER_LEVEL_8 1 2 full UART_TRIGGER_LEVEL_14 buffer_depth 2 default UART_IOCTL...

Page 37: ...g or an overrun error the read call returns 0 and the internal RX queue is flushed 5 5 4 Limitations 8 data bits only 1 stop bit only No hardware flow control support 5 6 UART32 5 6 1 Description This driver software for the UART32 IP 104 513 RD1 handles the setup and transfer of serial data to memory This is a high speed receive only UART 5 6 2 RTEMS API This API represents the driver interface o...

Page 38: ..._5M 5 MBaud UART32_IOCTL_BAUDRATE_2M 2 MBaud UART32_IOCTL_BAUDRATE_1M 1 MBaud UART32_IOCTL_BAUDRATE_115200 115200 Baud 5 6 2 2 Enum rtem_uart32_ioctl_endian_e Enumerator for the endianness of the DMA transfer Enumerator Description UART32_IOCTL_ENDIAN_BIG Big endian UART32_IOCTL_ENDIAN_LITTLE Little endian 5 6 2 3 Function int open Opens access to the requested UART32 Upon each open call the devic...

Page 39: ...1 See errno values errno values EINVAL Invalid options 5 6 2 5 Function ssize_t read Read data from the UART32 The call block until all data has been received from the UART32 or an error has occurred If any error condition occurs the read will return zero bytes Note Given buffer must be aligned to CPU_STRUCTURE_ALIGNMENT and the size must be a multiple of CPU_STRUCTURE_ALIGNMENT It is recommended ...

Page 40: ...criptor received at open cmd int in Command to send val uint32_t uint32t in out Value to write or a pointer to a buffer where data will be written Command table Type Direction Description UART32_SET_BAUDRATE_IOCTL uint32_t in Sets the baudrate for the UART32 see 5 6 2 1 UART32_SET_ENDIAN_IOCTL uint32_t in Sets the endian for the transfer see 5 6 2 2 UART32_GET_BURST_SIZE_IOCTL uint32_t out Get the...

Page 41: ...res Inclusion of bsp uart32_rtems h is required for accessing the UART32 5 6 4 Limitations The driver has limited UART functionality and can only receive data Data length is always 8 bits no parity check and only 1 stop bit is used The receive buffer must be aligned to CPU_STRUCTURE_ALIGNMENT and the size must be a multiple of CPU_STRUCTURE_ALIGNMENT include bsp h include fcntl h include unistd h ...

Page 42: ...ccess to the driver The device can only be opened once at a time Argument name Type Direction Description filename char in The absolute path to the file that is to be opened Mass memory device is defined as MASSMEM_DEVICE_NAME oflags int in Device must be opened by exactly one of the symbols defined in Table 5 1 Return value Description 0 A file descriptor for the device 1 see errno values errno v...

Page 43: ...o values errno values EBADF The file descriptor fd is not an open file descriptor EINVAL The whence argument is not a proper value or the resulting file offset would be negative for a regular file block special file or directory EOVERFLOW The resulting file offset would be a value which cannot be represented correctly in an object of type off_t 5 7 2 4 size_t read Reads requested size of bytes fro...

Page 44: ...ection Description fd int in File descriptor received at open buf void in Character buffer to read data from nbytes size_t in Number of bytes to write from buf Return value Description 0 Number of bytes that were written 1 see errno values errno values EBADF The file descriptor fd is not an open file descriptor EINVAL Page offset set in lseek is out of range or nbytes is too large and reaches a pa...

Page 45: ...n value Description 0 Status register value 5 7 2 6 4 Read control status data Return value Description 0 Always 5 7 2 6 5 Read EDAC register data Return value Description 0 Always 5 7 2 6 6 Read ID Command Type Direction Description MASSMEM_IO_RESET Command Type Direction Description MASSMEM_IO_READ_STATUS_DATA uint32_t out Command Type Direction Description MASSMEM_IO_READ_CTRL_STATUS uint8_t ou...

Page 46: ... was successful 1 Read operation failed 5 7 2 6 9 Program spare area Programs the spare area from the given data Return value Description 0 Program operation was successful 1 Program operation failed Command Type Direction Description MASSMEM_IO_ERASE_BLOCK uint32_t in Block number Command Type Direction Description MASSMEM_IO_READ_SPARE_AREA uint8_t in out Of type massmem_ioctl_spare_area_args_t ...

Page 47: ...ed in order to clear the page to its reset value Note that the whole block is erased not only the page It is the user application s responsibility to make sure any data the needs to be preserved after the erase block operation must first be read and rewritten after the erase block operation with the new page information 5 7 3 1 2 Usage The RTEMS driver must be opened before it can access the mass ...

Page 48: ...o initialise the driver at boot up CONFIGURE_APPLICATION_NEEDS_MASSMEM_FLASH_DRIVER must be defined for using the driver This will automatically initialise the driver at boot up 5 7 4 Limitations The TCM mass memory interface can currently only handle multiple consecutive RMAP write commands of size 1200 bytes or below include bsp h include fcntl h include unistd h include errno h include bsp mass...

Page 49: ...gh multiple accesses for data transaction is allowed only one access per unique device name is valid Device name must be set with a logical number as described in usage description in subchapter 5 8 3 1 Argument name Type Direction Description filename char in Device name to register to for data transaction oflags int in Device must be opened by exactly one of the symbols defined in Table 5 2 Retu...

Page 50: ... Direction Description fd int in File descriptor received at open buf void in Character buffer where to store the packet nbytes size_t In Packet size in bytes Must be between 0 and SPWN_MAX_PACKET_SIZE bytes Return value Description 0 Received size of the actual packet Can be less than nbytes 1 see errno values errno values EBADF The file descriptor fd is not an open file descriptor EINVAL buf siz...

Page 51: ...evice and therefore all file descriptors registered to it Return value Description 0 Given mode was set 1 see errno values errno values EINVAL Invalid mode 5 8 3 Usage 5 8 3 1 RTEMS 5 8 3 1 1 Overview The driver provides SpaceWire link setup and data transaction via the SpaceWire device Each application that wants to communicate via the SpaceWire device must register with a logical address The log...

Page 52: ...ffer in the following way uint8_t __attribute__ aligned SPWN_RX_PACKET_ALIGN_BYTES buf_rx PACKET_SIZE 5 8 3 1 2 Usage The application must first register to a device name before it can be accessed for data transaction Once registered via function open all provided operations can be used as described in the subchapter 5 8 2 Additionally if desired the access can be closed when not needed Figure 5 6...

Page 53: ...uired for retrieving error values on failures Inclusion of bsp spacewire_node_rtems h is required for driver related definitions Inclusion of bsp bsp_confdefs h is required to initialise the driver at boot up CONFIGURE_APPLICATION_NEEDS_SPACEWIRE_DRIVER must be defined for using the driver This will automatically initialise the driver at boot up include bsp h include fcntl h include unistd h inclu...

Page 54: ...cted on a pin Reading the time of the timestamp requires interaction with the SCET and exact register address depends on the current board configuration One SCET sample register is shared by all GPIOs 5 9 1 3 RTEMS differential mode In RTEMS finally a GPIO pin can also be set to operate in differential mode on output only This requires two pins working in tandem and if this functionality is enable...

Page 55: ...ctual number of devices available depends on the current hardware configuration flags int in Access mode flag O_RDONLY O_WRONLY or O_RDWR Return value Description Fildes A file descriptor for the device on success 1 See errno values errno values EALREADY Device is already open EINVAL Invalid options 5 9 2 2 Function int close Closes access to the GPIO pin Argument name Type Direction Description f...

Page 56: ...lected on the pin until it is set in output mode Argument name Type Direction Description fd int in File descriptor received at open buf const void in Pointer to character buffer to get the write data from count size_t in Number of bytes to write must be set to 1 Return value Description 0 Number of bytes that were written 1 See errno values errno values EINVAL Invalid options 5 9 2 5 Function int...

Page 57: ... out Get timestamp enable status of the pin 0 timestamp disabled 1 timestamp enabled GPIO_IOCTL_SET_TIMESTAMP_ENABLE uint32_t in Set timestamp enable configuration of the pin 0 timestamp disabled 1 timestamp enabled GPIO_IOCTL_GET_DIFF_MODE uint32_t out Get differential mode status of the pin 0 normal single ended mode 1 differential mode GPIO_IOCTL_SET_DIFF_MODE uint32_t in Set differential mode ...

Page 58: ...CATION_NEEDS_GPIO_DRIVER define CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER define CONFIGURE_APPLICATION_NEEDS_CONSOLE_DRIVER define CONFIGURE_USE_IMFS_AS_BASE_FILESYSTEM define CONFIGURE_MAXIMUM_DRIVERS 15 define CONFIGURE_MAXIMUM_SEMAPHORES 20 define CONFIGURE_LIBIO_MAXIMUM_FILE_DESCRIPTORS 30 define CONFIGURE_RTEMS_INIT_TASKS_TABLE define CONFIGURE_MAXIMUM_TASKS 20 define CONFIGURE_INIT include bs...

Page 59: ...n due to error in the incoming telecommand Telecommand frame buffer errors Telecommand frame buffer overflow Telecommand successfully received 5 10 2 RTEMS API This API represents the driver interface from a user application s perspective for the RTEMS driver The driver functionality is accessed through the RTEMS POSIX API for ease of use In case of failure on a function call errno value is set fo...

Page 60: ... the TM frame vcf_flag 1 The OCF flag Mcfc 8 The master channel frame counter Vcfc 8 The virtual channel frame counter tr_frame_sec_head_flag 1 The transfer frame secondary header flag tr_frame_sync_flag 1 The transfer frame sync flag tr_frame_packet_ord_flag 1 The transfer frame packet order flag segment_length_id 2 The segment length id first_header_pointer 11 The first header pointer data_field...

Page 61: ... struct for DMA descriptors The elements of the struct are described below Element Type Description desc_no uint32_t The descriptor number 0 31 desc_config uint32_t The configuration of the DMA descriptor desc_adress uint32_t The configuration of the DMA address descriptor 5 10 2 4 Data type tm_config_t This datatype is a struct for configuration of the TM path The elements of the struct are descr...

Page 62: ...ments of the struct are described below Element Type Description tc_derandomizer_bypassed uint8_t Bypassing of TC derandomizer 0 No bypass 1 Bypass 5 10 2 6 Data type tc_status_t This datatype is a struct to store status parameters of the TC path The elements of the struct are described below Element Type Description tc_frame_cnt uint8_t Number of received TC frames The counter will wrap around af...

Page 63: ... this field at the end Return value Description 0 A file descriptor for the device on success 1 see errno values errno values EBUSY If device already opened EPERM If wrong permissions ENOENT Bad file descriptor 5 10 2 8 int close Closes access to the device Argument name Type Direction Description Fd int in File descriptor received at open Return value Description 0 Device closed successfully 1 se...

Page 64: ... blocking until a Telecommand Transfer Frame is received Argument name Type Direction Description Fd int in File descriptor received at open Buf void in Character buffer where read data is returned Nbytes size_t in Number of bytes to write from the Return value Description 0 Number of bytes that were read 1 see errno values errno values EINVAL Wrong arguments EIO A physical access on the device fa...

Page 65: ...isables interrupts in the CCSDS IP CCSDS_GET_IE_CONFIG dev ccsds uint32_t Gets the configuration of the enabled disabled interrupts CCSDS_SET_DMA_DESC dev ccsds tm dma_descriptor_t Configures a DMA descriptor in the range 0 31 See 5 10 2 3 CCSDS_GET_DMA_DESC dev ccsds tm dma_descriptor_t Returns the configuration of a DMA descriptor in the range 0 31 See 5 10 2 3 CCSDS_GET_TM_STATUS dev ccsds tm u...

Page 66: ...be fetched by DMA transfer by writing to dev ccsds tm 5 10 3 2 Receive Telecommands 1 Open the device dev ccsds tm dev ccsds tc and dev ccsds Set up the TC path by ioctl call CCSDS_SET_TC_CONFIG on device dev ccsds tc or or ioctl CCSDS_INIT on device dev ccsds 2 Enable the different interrupts to be generated by ioctl CCSDS_SET_IE_CONFIG 3 Do a read from dev ccsds tc This call will block until a n...

Page 67: ...ons need to be adjusted as well Note also that the temperature equation require the 3V3 mV value HK channel Formula Temp m C Temp_mV ADC_value 2500 2 24 Temp_mC 1000 3V3_mV Temp_mV Temp_mV 1210 0 00385 Temp_mV 3300 Iin mA Iin_mA ADC_value 5000 2 24 Vin mV Vin_mV ADC_value 20575 2 24 3V3 mV 3V3_mV ADC_value 5000 2 24 2V5 mV 2V5_mV ADC_value 5000 2 24 1V2 mV 1V2_mV ADC_value 2525 2 24 5 11 2 RTEMS A...

Page 68: ...time only read access is allowed and only blocking mode is supported Argument name Type Direction Description Pathname const char in The absolute path to the ADC to be opened ADC device is defined as ADC_DEVICE_NAME Flags int in Access mode flag only O_RDONLY is supported Return value Description Fd A file descriptor for the device on success 1 See errno values errno values EEXISTS Device already ...

Page 69: ...1 see errno values errno values EPERM Device not open EINVAL Invalid number of bytes to be read ADC data buffer bit definition Description 31 8 ADC value 7 4 ADC status 3 0 Channel number 5 11 2 5 Function int ioctl Ioctl allows for more in depth control of the ADC IP like setting the sample mode clock divisor etc Argument name Type Direction Description Fd int in File descriptor received at open ...

Page 70: ...C_DISABLE_CHANNEL uint32_t in Disable specified channel number to be included when sampling Minimum 0 and maximum 15 Return value Description 0 Command executed successfully 1 see errno values errno values RTEMS_NOT_DEFINED Invalid IOCTL EINVAL Invalid value supplied to IOCTL 5 11 3 Usage The following define needs to be set by the user application to be able to use the ADC CONFIGURE_APPLICATION_N...

Page 71: ...as 32 768 bytes of 8 bits EDAC is implemented on a byte basis meaning that half the address space is filled with checksums for correction It s a strong correction which corrects 1 or 2 bit errors on a byte and detects multiple The table below presents the address space defined as words 16 384 bytes can be used The address space is divided into two sub groups as product and user address space inclu...

Page 72: ...n a function call the errno value is set for determining the cause 5 12 2 1 Enum rtems_spi_ram_edac_e Enumerator for the error correction and detection of the SPI RAM Enumerator Description SPI_RAM_IOCTL_EDAC_ENABLE Error Correction and Detection enabled SPI_RAM_IOCTL_EDAC_DISABLE Error Correction and Detection disabled 5 12 2 2 Function int open Opens access to the requested SPI RAM Argument name...

Page 73: ...Must be a multiple of 4 Return value Description 0 Number of bytes that were read 1 See errno values errno values EINVAL Invalid options 5 12 2 5 Function ssize_t write Write data into the SPI RAM The call block until all data has been written into the SPI RAM Argument name Type Direction Description fd int in File descriptor received at open buf void in Pointer to character buffer to read data fr...

Page 74: ...n Command table Type Direction Description SPI_RAM_SET_EDAC_IOCTL uint32_t in Configures the error correction and detection for the SPI RAM see 5 12 2 1 SPI_RAM_SET_DIVISOR_IOCTL uint32_t in Configures the serial clock divisor SPI_RAM_GET_EDAC_STATUS_IOCTL uint32_t out Get EDAC status for previous read operations SPI_RAM_UNLOCK_MEMORY_IOCTL uint32_t in Unlocks system memory for writing The input v...

Page 75: ...close ioctl Inclusion of errno h is required for retrieving error values on failures Inclusion of bsp spi_ram_rtems h is required for accessing the SPI_RAM include bsp h include fcntl h include unistd h include errno h include bsp spi_ram_rtems h define CONFIGURE_APPLICATION_NEEDS_SPI_RAM_DRIVER include bsp bsp_confdefs h include rtems confdefs h define CONFIGURE_INIT rtems_task Init rtems_task_ar...

Page 76: ...ing a package from the OBC S TM to the TCM S TM or vice versa the routing address will be 1 3 In addition to this each end node OBC S TM or TCM S TM has one or more logical address es to help distinguish between different applications or services running on the same node The logical address complements the path address and must be included in a SpaceWire packet Example If a packet is to be sent fr...

Page 77: ...e SpaceWire network according to the current TCM S TM configuration TM is received from other nodes on the SpaceWire network The TCM S TM supports both live TM transmissions directly to ground as well as storage of TM to the Mass Memory for later retrieval or download to ground during ground passes The TCM S TM is highly configurable to be adaptable to different customer needs and missions and cur...

Page 78: ...each specific command Note The TCM S TM uses the RMAP Transaction ID to separate between outstanding replies to different units When several nodes are addressing the TCM S TM they need to be assigned a unique transaction id range to ensure a correct system behaviour To allow for a similar transaction identification throughout the system the TCM S TM uses the Transaction ID range 0x0000 0x0FFF in a...

Page 79: ...artition x MMReadPointer 0xFF 0x0500020x R W Position of the readpointer for partition x MMPartitionConfig 0xFF 0x0500030x R Configuration of partition x MMPartitionSpace 0xFF 0x0500040x R Reads available space in partition x MMDownloadPartitionData 0xFF 0x0500050x W Downloads partition x data via telemetry 7 3 2 Output The TCM S TM publishes data to other nodes according to the address map below ...

Page 80: ...e Error Counter Field Control 0x00 Disabled 0x01 Enabled 3 UINT8 Master Frame Control 0x00 Disabled 0x01 Enabled 4 UINT8 Idle Frame Control 0x00 Disabled 0x01 Enabled 5 UINT8 CLCW Control 0x00 Disabled 0x01 Enabled 6 UINT8 Convolutional Encoding Control 0x00 Disabled 0x01 Enabled 7 UINT8 Pseudo Randomization Control 0x00 Disabled 0x01 Enabled 7 4 3 TMControl Enables disables generation of telemetr...

Page 81: ...e Default 7 4 7 TMPRControl Controls the Pseudo Randomization for transfer frames Table 7 11 TMPRControl data Byte Type Description 0 UINT8 0x00 Disable Default 0x01 Enable 7 4 8 TMOCFControl Controls Operational Control Field inclusion in TM Transfer frames Table 7 12 CLCW data Byte Type Description 0 UINT8 0x00 Disable 0x01 Enable Default 7 4 9 TMCEControl Controls the Convolutional Encoding for...

Page 82: ...Type Description 0 UINT8 0x00 No timestamping Default 0x01 Take a timestamp every time frame sent 0x02 Take a timestamp every 2 nd time frame sent 0xFF Take a timestamp every 255 th time frame sent 7 4 12 TMSend Sends telemetry to the TM path on virtual channel 0 The data must contain at least one telemetry PUS Packet Table 7 16 TMSend data Byte Type Description 0 nn Array of UINT8 Data containing...

Page 83: ... UINT16 Regulated 1V2 voltage mV 8 UINT16 Input current mA 10 UINT16 Temperature mºC 12 UINT32 SCET seconds 16 UINT8 S W version 17 UINT8 CPU Parity Errors 18 UINT8 Watchdog trips 19 UINT8 Critical SDRAM EDAC Single Errors 20 UINT8 Other SDRAM EDAC Single Errors 21 UINT8 Critical SDRAM EDAC Multiple Errors 22 UINT8 Other SDRAM EDAC Multiple Errors 7 4 16 SCETTime Reads sets the SCET time Any adjus...

Page 84: ...lator as reference and outputs a PPS at integer seconds Slave mode The SCET is synchronized to an external PPS and outputs no PPS Table 7 21 SCETConfig data Byte Type Description 0 UINT32 Configuration of SCET mode see above 0 Free running mode default 1 Master mode 2 Slave mode 7 4 18 ErrorStatus Reads the error status data Table 7 22 ErrorStatus data Byte Type Description 0 UINT8 CPU Parity Erro...

Page 85: ...ove 3 UINT8 Chip 0 status see above 4 UINT8 EDAC chip status see above 5 UINT8 Controller status Bit 7 Busy command in progress when high Bit 6 Reserved Bit 5 Reset done Bit 4 Read ID done Bit 3 Erase block done Bit 2 Read page setup done Bit 1 Read status done Bit 0 Program page done 6 UINT8 Chip ID Chip 3 7 UINT8 Chip ID Chip 2 8 UINT8 Chip ID Chip 1 9 UINT8 Chip ID Chip 0 10 UINT8 Chip ID EDAC ...

Page 86: ... the data in the partition 15 UINT8 Priority during download 0 Highest priority 16 UINT16 The data source identifier for the partition Can be used to set a custom identifier of a data producer to a partition Setting of this value is not required to successfully configure a partition 7 4 25 MMPartitionSpace Reads the space available in the specified partition Please note that due to the nature of t...

Page 87: ...UART 7 5 Telemetry The TCM S TM supports a format of TM Transfer Frames described in RD8 7 6 Telecommands The TCM S TM supports a format of TC Transfer Frames described in RD9 7 7 ECSS standard service The TCM S TM supports a subset of the services described in RD4 7 7 1 PUS 1 Telecommand verification service The TCM S TM performs a verification of APID of the incoming TC If the verification fails...

Page 88: ...ble 7 35 CPDU Command 2 3 Output Line ID Duration 0 11 1 octet 0 7 1 octet The duration is a multiple of the CPDU_DURATION_UNIT D defined to 12 5 ms as detailed below Table 7 36 CPDU Duration Duration in bits Duration in time ms 000 1 x D 12 5 001 2 x D 25 010 4 x D 50 011 8 x D 100 100 16 x D 200 101 32 x D 400 110 64 x D 800 111 128 x D 1600 Note The APIDs reserved for the CPDU are 1 9 for futur...

Page 89: ...terface 0 0xBA000000 GPIO 0xB6000000 Reserved for ADC controller 1 0xB5000000 ADC controller 0 0xB4000000 Reserved 0xB3000000 Mass memory flash controller TCM S TM only 0xB2000000 System flash controller 0xB1000000 Reserved 0xB0000000 NVRAM controller 0xAC000000 Reserved for PCIe 0xAB000000 Reserved for CAN 0xAA000000 Reserved for USB 0xA9000000 0xA3000000 Reserved 0xA2000000 Reserved for redundan...

Page 90: ...2 Spacewire Spacewire interrupt 23 CCSDS CCSDS interrupt 24 Ethernet Ethernet MAC interrupt signal 25 GPIO GPIO interrupt 26 SPI 0 Serial Peripheral interface 27 Ready to use reserved for SPI 1 28 Ready to use reserved for custom adaptation 29 Ready to use reserved for custom adaptation 30 Ready to use reserved for custom adaptation 8 3 SCET timestamp trigger sources Some of the peripherals in the...

Page 91: ...s for software images is given in Table 8 4 The first two 32 bit words of the image are expected to be a header with image size and an XOR checksum see Table 8 5 If the size falls within the accepted range the bootrom loads the image to RAM while verifying the checksum The bootrom loads a table of bad blocks from the NVRAM If a flash block within the range to load from is marked as bad in the tabl...

Page 92: ...n All clock domain crossings are either handled via FIFOs or synchronized into the other clock domain Two serial flip flops are used to reduce possible metastability effects 8 6 Pulse command inputs The pulse command inputs on the breadboard can be used to force the board to reboot from a specific image Paired with the ability of the TCM S to decode PUS 2 CPDU telecommands without software interac...

Page 93: ... taken and put into the system A 32 bit vector indicating seconds since 1970 01 01 UTC 0x4 PRODUCT_ID 0x00 0x01 0x02 0x0F OBC S BB OBC S OBC SR With SPW router 3 ports 0x10 0x11 0x12 0x1F TCM S BB TCM S TCM S R With SPW router 3 ports 0x20 0xFF Reserved 0x8 SOC_VERSION Follows the methodology of release 0 1 0 Release X Y Z where X represent a major number 8bits where Y represent a minor number 8bi...

Page 94: ...n be used as an alternative to the soft reset described in 5 3 Note This button must not be used during an update of the SoC FPGA 9 2 JTAG RTL FPGA JTAG connector The following pins are available on the ST60 10P connector see Table 9 1 Table 9 1 JTAG pin outs Pin Signal name Description Pin 1 GND Ground Pin 2 RTL JTAG TDI Test Data In data shifted into the device Pin 3 RTL JTAG TRSTB Test Reset Pi...

Page 95: ...D Ground Pin 10 DEBUG JTAG TDI Debug Test data in Pin 11 DEBUG JTAG RX Debug UART RX Pin 12 DEBUG JTAG TX Debug UART TX Pin 13 VCC_3V3 Power supply Pin 14 DEBUG JTAG TMS Debug Test mode select Pin 15 VCC_3V3 Power supply Pin 16 DEBUG JTAG TDO Debug Test data out Pin 17 GND Ground Pin 18 DEBUG JTAG TCK Debug Test clock 9 4 SPW1 Spacewire The following pins are available on the nano D9 socket connec...

Page 96: ...tive pair with p1 Pin 7 SPW2_SIN_LVDS_N SpaceWire strobe in negative pair with p2 Pin 8 SPW2_SOUT_LVDS_P SpaceWire strobe out positive pair with p4 Pin 9 SPW2_DOUT_LVDS_P SpaceWire data out positive pair with p5 9 6 ANALOGS Analog input and 4xGPIO OBC S The following pins are available on the nanoD25 socket connector see Table 9 5 Table 9 5 ANALOGS 4xGPIO pin outs Pin Signal name Description Pin 1...

Page 97: ...t output Pin 2 GPIO1 Digital input output Pin 3 GPIO2 Digital input output Pin 4 GPIO3 Digital input output Pin 5 GPIO4 Digital input output Pin 6 GPIO5 Digital input output Pin 7 GPIO6 Digital input output Pin 8 GPIO7 Digital input output Pin 9 GPIO8 Digital input output Pin 10 GPIO9 Digital input output Pin 11 GPIO10 Digital input output Pin 12 GPIO11 Digital input output Pin 13 GND Board ground...

Page 98: ...n 7 UART1_RX_RS4XX_P UART Port 1 RX Pin 8 UART1_RX_RS4XX_N Pin 9 UART1_TX_RS4XX_P UART Port 1 TX Pin 10 UART1_TX_RS4XX_N Pin 11 UART2_RX_RS4XX_P UART Port 2 RX Pin 12 UART2_RX_RS4XX_N Pin 13 UART2_TX_RS4XX_P UART Port 2 TX Pin 14 UART2_TX_RS4XX_N Pin 15 GND Ground 9 9 COM35_RS4XX RS422 485 OBC S The following pins are available on the nanoD15 socket connector see Table 9 8 Table 9 8 COM35_RS4XX pi...

Page 99: ... Baseband data in RS422 Pin 6 SBAND_DIN_RS422_N Pin 7 SBAND_CIN_RS422_P Baseband clock in RS422 Pin 8 SBAND_CIN_RS422_N Pin 9 SBAND_SC_LOCK_IN_RS422_P Sub carrier lock in Pin 10 SBAND_SC_LOCK_IN_RS422_N Pin 11 SBAND_C_LOCK_IN_RS422_P Carrier lock in Pin 12 SBAND_C_LOCK_IN_RS422_N Pin 13 GND Pin 14 SBAND_HKCTRL1_TX_RS422_P TRX control housekeeping signaling Connects to TCM S UART3 Pin 15 SBAND_HKCT...

Page 100: ...nd clock in LVDS Pin 8 XBAND_CIN_LVDS_N Pin 9 XBAND_SC_LOCK_IN_RS422_P Sub carrier lock in RS422 Pin 10 XBAND_SC_LOCK_IN_RS422_N Pin 11 XBAND_C_LOCK_IN_RS422_P Carrier lock in RS422 Pin 12 XBAND_C_LOCK_IN_RS422_N Pin 13 GND Pin 14 XBAND_HKCTRL1_TX_RS422_P TRX control housekeeping signaling Connects to TCM S UART4 Pin 15 XBAND_HKCTRL1_TX_RS422_N Pin 16 XBAND_HKCTRL2_TX_RS422_P Reserved Pin 17 XBAND...

Page 101: ...me Description Pin 1 UMBI_DOUT_RS422_P Baseband data out Pin 2 UMBI_DOUT_RS422_N Pin 3 UMBI_COUT_RS422_P Baseband clock out Pin 4 UMBI_COUT_RS422_N Pin 5 UMBI_DIN_RS422_P Baseband data in Pin 6 UMBI_DIN_RS422_N Pin 7 UMBI_CIN_RS422_P Baseband clock in Pin 8 UMBI_CIN_RS422_N Pin 9 UMBI_SC_LOCK_IN_RS422_P Sub carrier lock in Pin 10 UMBI_SC_LOCK_IN_RS422_N Pin 11 UMBI_C_LOCK_IN_RS422_P Carrier lock i...

Page 102: ...2_N Pin 3 PULSE1_O_RS422_P Pin 4 PULSE1_O_RS422_N Pin 5 PULSE2_O_RS422_P Pin 6 PULSE2_O_RS422_N Pin 7 PULSE3_O_RS422_P Pin 8 PULSE3_O_RS422_N Pin 9 PULSE4_O_RS422_P Pin 10 PULSE4_O_RS422_N Pin 11 PULSE5_O_RS422_P Pin 12 PULSE5_O_RS422_N Pin 13 GND Pin 14 PULSE6_O_RS422_P Pin 15 PULSE6_O_RS422_N Pin 16 PULSE7_O_RS422_P Pin 17 PULSE7_O_RS422_N Pin 18 PULSE8_O_RS422_P Pin 19 PULSE8_O_RS422_N Pin 20 P...

Page 103: ...pgrade the FPGA firmware 1 Connect the FlashPro5 programmer via the 104470 FPGA programming cable assembly to connector 4 in Figure 3 1 2 Connect the power cables according to Figure 3 1 3 The updated FPGA firmware delivery from ÅAC should contain three files a The actual FPGA file with an stp file ending b The programmer file with a pro file ending c The programmer script file with a tcl file end...

Page 104: ...pad size The outline in the left upper corner of the drawing below corresponds to the FM version of the TCM S TM and OBC S TM boards Figure 11 1 The Sirius board mechanical dimensions 12 Environmental information The Sirius Breadboard is an engineering model and as such it is only intended for office usage Table 12 1 Environmental temperature ranges Environment Range Operating temperature EM 0 40 ...

Page 105: ...r debugging the PCBs LVTTL Low Voltage TTL Minicom Is a text based modem control and terminal emulation program NA Not Applicable NVRAM Non Volatile Random Access Memory OBC On Board Computer OS Operating System PCB Printed Circuit Board PCBA Printed Circuit Board Assembly POSIX Portable Operating System Interface PUS Packet Utilization Standard RAM Random Access Memory however modern DRAM has not...

Page 106: ...Document number 204911 Version Rev K Issue date 2016 10 11 Sirius Breadboard User Manual www aacmicrotec com Page 106 of 106 ...

Search results

Summary of Contents for Sirius

Reviews:

Related manuals for Sirius

Brands by name

Popular brands

AAC Microtec Sirius, User Manual

Search results

Summary of Contents for Sirius

Reviews:

Related manuals for Sirius

Brands by name

Popular brands