DRAM R/W Leadoff Timing
: 7/6
Chipset NA# Asserted
: Enabled
Fast RAS# To CAS# Delay
: 3
Pipeline Cache Timing
: Faster
DRAM Read Burst (EDO/FPM)
: x333/x444
Passive Release
: Enabled
DRAM Write Burst Timing
: x333
Delayed Transaction
: Enabled
Turbo Read Leadoff
: Disabled
DRAM Speculative Leadoff
: Disabled
Turn-Around Insertion
: Disabled
ISA Clock
: PCICLK/4
System BIOS Cacheable
: Disabled
Video BIOS Cacheable
: Disabled
8-bit I/O Recovery Time
: 3
16-bit I/O Recovery Time
: 2
Esc: Quit
:Select Item
Memory Hole At 15M-16M
: Disabled
F1 : Help
PU/PD/+/-:Modify
Peer Concurrency
: Enabled
F5 : Old Values
(Shift)F2 :Color
Chipset Special Featuires
: Disabled
F6 :Load BIOS Defaults
DRAM ECC/PARITY Select
: Parity
Auto
Pre-defined values for DRAM, cache... timing
Configuration
according to CPU type & system clock. When
this item is enabled, the pre-defined items will
become SHOW-ONLY.
DRAM Timing
The DRAM speed is controlled by the DRAM
timing Registers. The timings programmed into
this register are dependent on the system design.
DRAM RAS#
DRAM must continually be refreshed or it will lose
Precharge Time
its data. Normally, DRAM is refreshed entirely as
the result of a single request. This option allows
you to determine the number of CPU clocks
allocated for the Row Address Strobe to
accumulate its charge before the DRAM is
refreshed. If insufficient time is allowed, refresh
may be incomplete and data lost.
Fast RAS# to
When DRAM is refreshed, both rows and columns
CAS# Delay
are addressed separately. This setup item allows
you to determine the timing of the transition from
RAS to Column Address Strobe (CAS).
DRAM Read
This sets the timing for burst mode read (or writes)
Burst (EDO/FPM)
from DRAM. Burst read and write requests are
DRAM Write
generated by the CPU in four separate parts.
Burst Timing
The first part provides the location within the
DRAM where the read or write is to take place
while the remaining three parts provide the
actual data. The lower the timing numbers, the
faster the system will address memory.
ISA Clock
This item allows you to select the PCI clock type.
Choices are PCI CLK/3; PCI CLK/4
System BIOS
When enabled, accesses to the system BIOS
Cacheable
ROM addressed at F0000H-FFFFFH are cached,
provided that the cache controller is enabled.
