Hardware Development Guide of Module Product
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43
MF206A
Figure 3–11 Power-off Sequence Chart of Module
POWER_ON
T5
T4
VPH_PWR
USB_VBUS
Table 3–11 Power-on/Power-off Time
Parameter
Description
Min
Typical
Max
Unit
T1
From powering on VPH_PWR to
establishing USB_VBUS
0
0.5
1
second
T2
From powering on VPH_PWR to Power-on
taking effect
1
1.5
--
second
T3
The period that the Power-on signal for
power on operation is kept on the low PWL
0.05
0.1
--
second
T4
The period that the Power-on signal for
power off operation is kept on the low PWL
4
5
--
second
T5
From the releasing the Power-on button for
power off operation to the power off of
VPH_PWR and USB_VBUS
1
2
--
second
3.12.3
Resetting Flow
The PON_RST_N reset signal of module is the increasing resetting, so it is reset after decreasing this PIN by
100ms. Figure 3-13 is the module resetting flow. Figure 3-14 is the timing of resetting module.