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Le51HE001V

QLSLAC

Evaluation Board, Revision E User’s Guide

Rev. A, Ver. 2

October 2, 2007

Document Number: 080800

Содержание Le51HE001V

Страница 1: ...Le51HE001V QLSLAC Evaluation Board Revision E User s Guide Rev A Ver 2 October 2 2007 Document Number 080800...

Страница 2: ...and other information appearing in this publication are subject to change by Zarlink without notice No warranty or guarantee express or implied is made regarding the capability performance or suitabil...

Страница 3: ...SETUP AND CONNECTIONS 7 3 1 Overview 7 3 2 Digital Interface 8 3 3 Power Connections 9 3 4 Analog Interface and SLIC Device Control 9 3 5 Device Socket Orientation 10 CHAPTER 4 SOFTWARE OPERATION 11...

Страница 4: ...Le51HE001V Eval Board User Guide ii Zarlink Semiconductor Inc This page left intentionally blank...

Страница 5: ...nterface option as well as the PCM MPI interface The Le58QL02 021 031 series supports only the PCM MPI interface Within each of the device series there are different pin out and package options The cu...

Страница 6: ...Le51HE001V Eval Board User Guide 2 Zarlink Semiconductor Inc Figure 1 1 Le51HE001V Evaluation Board Revision E Silk Screen...

Страница 7: ...ovided from the external MCLK input or the device may internally derive the signal from the PCM PCLK clock input In GCI mode the master clock is derived from the DCL pin If the internal clock is deriv...

Страница 8: ...jumper positions Figure 2 2 Jumpers JDVCC and JAVCC As shown in Figure 2 2 above shorting pin 1 to 2 selects the DVCC and AVCC supplies for the QLSLAC device to be supplied via the SLAC_VCC connection...

Страница 9: ...has a trace connecting it to the adjacent row of pins in the breadboard area An example of this is shown in Figure 2 3 below Figure 2 3 VIN VOUT BNC Trace Table 2 4 PCM Test Points PCM Test Point Desc...

Страница 10: ...Le51HE001V Eval Board User Guide 6 Zarlink Semiconductor Inc This page intentionally left blank...

Страница 11: ...nnected to the Le51HE001V Evaluation Board via a 20 pin ribbon cable and 2 BNC cables In Figure 3 1 the Le51HE001V Evaluation Board is connected to the VP Demo Board via the 50 pin connector SPA The h...

Страница 12: ...nt is provided through either the VP Demo Board or the ACIF2 A board 3 2 DIGITAL INTERFACE All PCM MPI interface signals pass through IFB0 the 50 pin connector from either the ACIF2 A board or the VP...

Страница 13: ...e H1 H2 H3 and H4 headers These headers provide external off board control of the SLIC device and monitor the DETECT signal when the SLIC Device Evaluation Board has its own control select jumpers set...

Страница 14: ...QLSLAC device is oriented such that pin 1 of the device is towards the right hand side of the board near the bottom refer to Figure 1 1 on page 1 2 The pin numbers 11 12 22 33 34 and 44 are printed o...

Страница 15: ...Return Loss Transmit and Receive attenuation Distortion Transmit and Receive path equalization Two wire Stability For a more detailed description refer to the WinSLAC2 Software User s Guide PID 08077...

Страница 16: ...Le51HE001V Eval Board User Guide 12 Zarlink Semiconductor Inc This page intentionally left blank...

Страница 17: ...IF2 A Board 2 Connect 5 V and GND to the ACIF board 3 Connect the banana jacks of the Le51He001V to the supplies and power up both boards 4 On the PC start the WinACIF program and select device 5 Clic...

Страница 18: ...button e Enter Gain 1 01 11 f Click on the Write Coeff button g Click on the Wrt Rd X Filter button h Enter 1 for the decimal value on each channel i Click on the Write button j Click on the Wrt Rd R...

Страница 19: ...BNC Independently changing the AX AR and Z Gain values and writing that value s to the QLSLAC will affect the output signal therefore allowing the user to see how these blocks can affect a signal Eith...

Страница 20: ...Channel Register menu do as follows a Disable channels 1 and 3 b Enable channels 2 and 4 5 From the Wrt Rd SLIC IO Direction menu do as follows a Leave IOD1 through IOD5 set to 0 b Click on the Write...

Страница 21: ...conductor Inc 6 Le51HE001V EVALUATION BOARD SCHEMATIC AND BOM 6 1 EVALUATION BOARD SCHEMATIC AND BOM The schematic for the Le51HE001V Evaluation Board revision E and the Bill of Materials are attached...

Страница 22: ...Le51HE001V Eval Board User Guide 18 Zarlink Semiconductor Inc...

Страница 23: ...face It passes user control information to internal blocks of the QLSLAC device and passes status information from the internal blocks to the user PCM Pulse Code Modulation The modulation scheme invol...