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CLM920_NC3_LTE Module hardware manual
Shanghai Yuge Information Technology co., LTD
- 51 -
116
MCLK
D0
I2S master
clock
VOH
1.35
1.8
2
The default
output is
12.288M
VOL
0
0.45
3.16 ADC interface
The CLM920 NC3 provides two analog-to-digital converter interfaces to read the voltage
value. The ADC interface input voltage cannot exceed VBAT. It is recommended that the
ADC pin be input with a voltage divider circuit.
Table 3-23 ADC Pin Definitions
Pin
Signal
name
I/O
Description
Level value (V)
Remarks
Min Typical Max
44
ADC1
Analog to digital
converter
interface 0
VIN
0.3
VBAT ADC
resolution
15Bits
45
ADCO
Analog to digital
converter
interface 0
VIN
0.3
VBAT ADC
resolution
15Bits
3.17 RF interface
CLM920 NC3 module provides three-way antenna interface, one main set antenna
interface, which is responsible for 4G, 3G, 2G signals of transceiver module, one-way
diversity antenna interface, responsible for receiving 4G, 3G signals, and signal degradation
caused by multi-path under high-speed movement Signals can be enhanced by adding
diversity antennas, as well as a GNSS antenna interface for GPS, Beidou, GLONASS,
GALILEO signal reception, which can provide positioning solutions for users. Three-way
antenna interface impedance is 50 ohms.
Table 3-24 Antenna interface pin definition
Pin Signal name
I/O
Description
Remarks
49
ANT_MAIN IO
Main antenna interface
50
Ω
characteristic impedance
35
ANT_DIV
AI
Diversity antenna interface
50
Ω
characteristic impedance
47
ANT_GNSS AI
GNSS antenna interface
50
Ω
characteristic impedance