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App
Index
7-3
IM WT3001E-17EN
Status Reports
7.2 Status Byte
Status Byte
7
6 ESBMAVEES EAV 1
0
RQS
MSS
Bits 0, 1, and 7
Not used (always 0)
Bit 2 EAV (Error Available)
Set to 1 when the error queue is not empty. In other words, this bit is set to 1 when an
error occurs. See the page 7-9.
Bit 3 EES (Extend Event Summary Bit)
Set to 0 when the logical product of the extended event register and the corresponding
enable register is 1. In other words, this bit is set to 1 when an event takes place inside
the instrument. See the page 7-7.
Bit 4 MAV (Message Available)
Set to 1 when the output queue is not empty. In other words, this bit is set to 1 when
there are data to be transmitted. See the page 7-9.
Bit 5 ESB (Event Summary Bit)
Set to 0 when the logical product of the standard event register and the corresponding
enable register is 1. In other words, this bit is set to 1 when an event takes place inside
the instrument. See the page 7-5.
Bit 6 RQS (Request Service)/MSS (Master Status Summary)
Set to 1 when the logical AND of the status byte excluding Bit 6 and the service request
enable register is not 0. In other words, this bit is set to 1 when the instrument is
requesting service from the controller.
RQS is set to 1 when the MSS bit changes from 0 to 1, and cleared when serial polling is
carried out or when the MSS bit changes to 0.
Bit Masking
If you wish to mask a certain bit of the status byte so that it does not cause a SRQ, set
the corresponding bit of the service request enable register to 0. For example, to mask
bit 2 (EAV) so that service is not requested when an error occurs, set bit 2 of the service
request enable register to 0. This can be done using the
*SRE
command. To query
whether each bit of the service request enable register is 1 or 0, use
*SRE?
. For details
on the
*SRE
command, see chapter 6.