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16-49
IM 765601-01E
Communication Commands
3
2
1
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
App
Index
16.3.4 Source Event Register
Source Event Register
Event Register
:STATus:SOURce:EVENt?
Condition Register
:STATus:SOURce:CONDition?
SSB
SSB
ILC
ILC EMR2
EMR2
LHI2
LHI2
LLO2
LLO2
RDY2
RDY2
TRP2
EOS2
LHI1
LHI1
LLO1
LLO1
RDY1
RDY1
TRP1
EOS1
14
15
13 12 11 10
9
8
14
15
13 12 11 10
9
8
EMR1
EMR1
6
7
5
4
3
2
1
0
6
7
5
4
3
2
1
0
Bit 15 SSB (Start Sampling Error)
The bit in the condition register temporarily set to 1 if
an overlapped sweep start is applied before the sweep
operation is completed and a sampling error occurs.
The bit in the event register is set to 1 when the
condition register bit changes from 0 to 1.
Bit 14 ILC (Inter Locking)
The bit in the condition register is set to 1 during
interlock. The bit in the event register is set to 1 when
the condition register bit changes from 0 to 1.
Bit 13 EMR2 (CH2 Emergency)
The bit in the condition register is set to 1 if the
temperature error or overcurrent protection of CH2 is
activated and the GS820 needs to be turned OFF. The
bit in the event register is set to 1 when the condition
register bit changes from 0 to 1.
Bit 12 TRP2 (CH2 Tripped)
The bit in the event register is set to 1 if a trip occurs
on CH2 and the output is turned OFF.
Bit 11 LHI2 (CH2 High Limiting)
The bit in the condition register is set to 1 if the high
limiter of CH2 is activated. The bit in the event register
is set to 1 when the condition register bit changes from
0 to 1.
Bit 10 LLO2 (CH2 Low Limiting)
The bit in the condition register is set to 1 if the low
limiter of CH2 is activated. The bit in the event register
is set to 1 when the condition register bit changes from
0 to 1.
Bit 9 RDY2 (CH2 Ready for Sweep)
The bit in the condition register is set to 1 if the CH2
is ready to sweep and 0 if the sweep operation is in
progress. The bit in the event register is set to 1 when
the condition register bit changes from 0 to 1.
Bit 8 EOS2 (CH2 End of Sweep)
The bit in the condition register is set to 1 if the CH2
sweep operation is completed.
Bit 7
Not used (always 0)
Bit 6
Not used (always 0)
Bit 5 EMR1 (CH1 Emergency)
The bit in the condition register is set to 1 if the
temperature error or overcurrent protection of CH1 is
activated and the GS820 needs to be turned OFF. The
bit in the event register is set to 1 when the condition
register bit changes from 0 to 1.
Bit 4 TRP1 (CH1 Tripped)
The bit in the event register is set to 1 if a trip occurs
on CH1 and the output is turned OFF.
Bit 3 LHI1 (CH1 High Limiting)
The bit in the condition register is set to 1 if the high
limiter of CH1 is activated. The bit in the event register
is set to 1 when the condition register bit changes from
0 to 1.
Bit 2 LLO1 (CH1 Low Limiting)
The bit in the condition register is set to 1 if the low
limiter of CH1 is activated. The bit in the event register
is set to 1 when the condition register bit changes from
0 to 1.
Bit 1 RDY1 (CH1 Ready for Sweep)
The bit in the condition register is set to 1 if the CH1
is ready to sweep and 0 if the sweep operation is in
progress. The bit in the event register is set to 1 when
the condition register bit changes from 0 to 1.
Bit 0 EOS1 (CH1 End of Sweep)
The bit in the condition register is set to 1 if the CH1
sweep operation is completed.
Bit Masking
To mask a bit in the source event register so that
it does not cause bit 1 (SSB) of the status byte to
change, set the corresponding bit in the source event
enable register to 0. Use the :STATus:SOURce:ENABle
command for this purpose.
Reading the Source Event Register
The contents of the source event register can be
read by the :STATus:SOURce:EVENt? command.
After the register is read, it is cleared. The contents
of the source condition register can be read by the
:STATus:SOURce:CONDition? command. Reading the
register does not change the contents of the register.
16.3 Status Reports