16-47
IM 765601-01E
Communication Commands
3
2
1
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
App
Index
Status Byte Operation
A service request is issued when bit 6 of the status
byte becomes 1. Bit 6 is set to 1 when any of the other
bits becomes a 1 (when the corresponding bit of the
service request enable register is also set to 1).
For example, if an event occurs and the logical AND
of the standard event register and the corresponding
enable register becomes a 1, then bit 5 (ESB) is set
to 1. In this case, if bit 5 of the service request enable
register is 1, bit 6 (MSS) is set to 1, thus requesting
service from the controller.
In addition, you can also check what type of event
occurred by reading the contents of the status byte.
Reading the Status Byte
The following two ways to read the contents of the
status byte:
Inquiry using the *STB? query
A *STB? query causes bit 6 to be a MSS bit. This
causes the MSS to be read. After completion of the
read-out, none of the bits in the status byte will be
cleared.
Serial Polling
Serial polling causes bit 6 to be a RQS bit. This causes
RQS to be read. After completion of the read-out,
only RQS is cleared. MSS cannot be read using serial
polling.
Clearing the Status Byte
There are no ways to clear all the bits of the status
byte. The bits that are cleared for each operation are
shown below.
When a query is made using the *STB? command
None of the bits are cleared.
When serial polling is executed
Only the RQS bit is cleared.
When a *CLS command is received.
Receiving the *CLS command will not clear the status
byte itself, but the contents of the standard event
register that affect the status byte. As a result, the
corresponding bits in the status byte are cleared,
except bit 4 (MAV), since the output queue cannot be
emptied by the *CLS command. However, the output
queue will also be cleared if the *CLS command is
received just after a program message terminator.
16.3.3 Standard Event Register
Standard Event Register
URQ
6
PON
7
5
4
3
2
1
0
CME EXE DDE QYE RQC OPC
Bit 7 PON (Power ON)
Set to 1 when the instrument is turned ON.
Bit 6 URQ (User Request)
Not used (always 0)
Bit 5 CME (Command Error)
Set to 1 when there is an error in the command syntax.
Example
Incorrectly spelled command name;
“9” used in octal data.
Bit 4 EXE (Execution Error)
Set to 1 when the command syntax is correct, but the
command cannot be executed in the current state of
the instrument.
Example
Parameters are outside the range.
Bit 3 DDE (Device Error)
Set to 1 when a command cannot be executed for
internal reasons other than a command syntax error
and command execution error.
Bit 2 QVE (Query Error)
Set to 1 when a query command is transmitted, but the
error queue is empty or the data are lost.
Example
No response data; data is lost due to
an overflow in the output queue.
Bit 1 RQC (Request Control)
Not used (always 0)
Bit 0 OPC (Operation Complete)
Set to 1 when the operation designated by the *OPC
command (see section 16.2.14) is completed.
Bit Masking
To mask a certain bit of the standard event register so
that it does not cause bit 5 (ESB) of the status byte to
change, set the corresponding bit of the standard event
enable register to 0.
For example, to mask bit 2 (QYE) so that ESB will not
be set to 1 even if a query error occurs, set bit 2 of the
standard event enable register to 0. This can be done
using the *ESE command. To inquire whether each bit
of the standard event enable register is 1 or 0, use the
*ESE?. For details on the *ESE command, see section
16.2.14.
16.3 Status Reports
