17-4
IM 701730-01E
Item
Description
Pulse Width:
Trigger occurs on the True/False width of the parallel pattern of multiple trigger
sources.
Parallel pattern is the AND of the status of the channels or the AND of the
window conditions of the channels.
Pulse>Time:
Trigger occurs when the width described above
is greater than Time.
Pulse<Time:
Trigger occurs when the width described above
is smaller than Time.
T1<Pulse<T2:
Trigger occurs when the width described above
is greater than T1 and smaller than T2.
Time Out:
Trigger occurs when the width described
exceeds Time.
Specified time:
1 ns to 1 s
Time accuracy
2
:
±
(0.5% of the setting
4
+ 1 ns)
Minimum time detection width: 2 ns (typical value
5
)
TV:
Activates a trigger on the video signal of various formats: NTSC, PAL, SECAM,
1080/60i, 1080/50i, 720/60p, 480/60p, 1080/25p, 1080/24p, 1080/24sF, and
1080/60p CH1 is the only input channel. Field number and line number
selectable.
• Condition A and Condition B are parallel patterns set using High, Low, and Don’t Care on
each channel CH1 to CH4
1
.
Trigger gate
Trigger can be activated only when the trigger condition is met when the input from the trigger
gate input terminal (TRIG GATE IN) is active.
Active level can be set to high or low.
1. Or CH1 and CH2 on the DL1720E
2. Under standard operating conditions (see section 17.11) after the warm-up and calibration. have been performed.
3. Under standard operating conditions (see section 17.11) after the warm-up.
4. The setting for T1<Pulse<T2 is the T2 value.
5. Typical value represents a typical or average value. It is not strictly warranted.
17.3 Time Axis
Item
Description
Time axis range
1 ns/div to 50 s/div (when the record length is greater than or equal to 10 kW)
1 ns/div to 5 s/div (when the record length is equal to 1 kW)
Time base accuracy
1
±
(0.005%)
Time axis precision
1
±
(0.005%+50ps+1digit)
2
.
External clock input
3
Connector type:
BNC
Maximum input voltage:
±
40 V (DC+ACpeak) or 28 Vrms when the frequency is 10 kHz or
Input frequency range:
40 Hz to 20 MHz (continuous clock only)
Sampling jitter:
±
1.25 ns or less
Minimum input amplitude:
0.1 VP-P(DL1735E/DL1740E/DL1740EL)
0.1 VP-P (when the
±
1 V range set on the DL1720E)
1 VP-P (when the
±
10 V range set on the DL1720E)
Threshold level:
±
2 V, setting resolution is 5 mV (on the DL1735E/DL1740E/
DL1740EL)
±
1 V, setting resolution: 5 mV (when the
±
1 V range set on the
DL1720E)
±
10 V, setting resolution: 50 mV (when the
±
10 V range set on the
DL1720E)
Input impedance:
Approximately 1 M
Ω
and approximately 20 pF
Minimum pulse width:
10 ns or more for High and Low.
1. Under standard operating conditions (see section 17.11) after the warm-up.
2. 1 digit is the amount that cannot be determined due to sampling error.
3. On the DL1745E/DL1740E/DL1740EL, the terminals are EXT CLOCK IN/EXT TRIG IN/TRIG GATE IN, and on the DL1720E
it is labeled EXT.
17.2 Trigger Section
