17-3
IM 701730-01E
Specifications
17
17.2 Trigger Section
Item
Description
Trigger mode
Auto, auto-level, normal, single, and single(N)
Trigger source
CH1 to CH4
1
(signal input from each input terminal), LINE (commercial power supply signal that
is connected), EXT (signal input from the EXT TRIG IN terminal (or the EXT terminal on the
DL1720E)).
Trigger coupling
CH1-CH4
1
:
DC/AC
EXT:
DC
HF rejection
Select the bandwidth limit with respect to the trigger source (OFF/DC to approx. 15 kHz or DC
to approx. 20 MHz) for each channel (CH1 to CH4
1
)
Trigger hysteresis
Select high or low for the trigger level hysteresis width for each channel (CH1 to CH4
1
)
Trigger level range
CH1-CH4
1
:
4 divisions from the screen center.
EXT:
±
2 V (DL1735E/DL1740E/DL1740EL)
±
1 V (when the
±
1 V range set on the DL1720E)
±
10 V (when the
±
10 V range set on the DL1720E)
Trigger level setting resolution CH1-CH4
1
:
0.01div
EXT:
5 mV (DL1735E/DL1740E/DL1740EL)
5 mV (when the
±
1 V range set on the DL1720E)
50 mV (when the
±
10 V range set on the DL1720E)
Trigger level accuracy
CH1-CH4
1, 2
:
±
(one di 10% of the trigger level)
EXT
3
:
±
(50 mV + 10% of the trigger level) (DL1735E/DL1740E/DL1740EL)
±
(50 mV + 10% of the trigger level) (
±
1 V range of the DL1720)
±
(500 mV + 10% of the trigger level) (
±
10 V range of the DL1720)
Probe attenuation setting for
1:1/10:1
external trigger
Trigger sensitivity
2
CH1-CH4
1
:
For DC-500 MHz, 1divP-P(DL1720E/DL1740E/DL1740EL)
For DC-350 MHz, 1divP-P(DL1735E)
EXT:
DC to 100 MHz 100 mVP-P (DL1735E/DL1740E/DL1740EL)
DC to 100 MHz 100 mVP-P (
±
1 V range of the DL1720E)
DC to 100 MHz 1 VP-P (
±
10 V range of the DL1720E)
Trigger position
Can be set in 1% increments of the display record length.
Trigger delay range
0 to 4 s
Hold off time range
80 ns to 10 s
Trigger slope
Rising, falling, rising and falling (for edge trigger)
Trigger type
Edge:
Activate the trigger on the edge of a single trigger source.
A->B(N):
Trigger occurs nth time condition B becomes true after condition A becomes
true.
Count:
1-10
8
Condition A:
Enter/Exit OR:
Condition B:
Enter/Exit OR:
A Delay B:
Trigger occurs first time condition B becomes true after specified delay following
condition A true.
Specified time:
3 ns to 5 s
Condition A:
Enter/Exit OR:
Condition B:
Enter/Exit OR:
OR:
Trigger occurs on the OR logic of the trigger conditions set to multiple trigger
sources.
Trigger conditions are Edge and Window, and Rise (IN), Fall (Out), or Don’t
Care can be set to each channel CH1 to CH4
1
.
Pattern:
Trigger occurs on the edge of the clock channel with respect to the True/False
condition of the parallel pattern set to multiple trigger sources.
If the clock channel is set to Don’t Care, trigger occurs on the Enter or Exit
condition of the True/False condition of the parallel pattern.
Parallel pattern is the AND of the state of each channel.
