App-1
IM 2560A-01EN
Appendix
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1
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8
9
10
11
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16
App
Index
Appendix 1 Block Diagram
Pt100
HI
LO
Low voltage-
current
output
terminals
Resistance
source circuit
Range switching circuit
Power
amplifier
+
−
Pre-
amp
Reference
voltage
Vref
DAC
PWM
ADC
INT RJ sensor
measurement
circuit
• DAC control
• Range/feedback
switching control
• Resistance source
control circuit
• INT RJ sensor
measurement
+
DAC code
generation
Value
smoothing
Correction
value
calculation
Ground side
FPGA
To the CPU
Isolated
side
Ground
side
Isolated side
FPGA
Isolated power supply
(OUTPUT 1)
Guard
Power amplifier
+
−
Pre-
amp
HI
LO
High voltage
output terminals
(OUTPUT 2)
Large current
output terminals
Power amplifier
+
−
Pre-
amp
HI
LO
(OUTPUT 2)
When the output is turned on or when the source value is changed, a source code for setting the DAC
is sent from the CPU/FPGA on the ground side to the FPGA on the isolated side. To the source code,
the FPGA on the isolated side applies overshoot suppression and rising slope control (smoothing) for
reducing inrush current for when a capacitive load is connected. Then, the FPGA sends the source
code to the DAC.
On the other hand, the high-speed PWM ADC is sequentially measuring reference voltage Vref and
zero level based on a high accuracy reference and the output of its own DAC. The source code is
compared and corrected with these values and continuously transferred from the FPGA on the isolated
side to the DAC. This method provides long-term stable DAC output.
The pre-amp employs a low-noise, high-precision amplifier that accurately amplifies the DAC output.
The power amplifier employs a power-transistor-based push-pull-output amplifier that enables sink
operation.
The 2560A does not use relays to invert the polarity for ranges other than 1000 V and 10 A, so glitches
due to polarity switching do not occur. The control system on the isolated side is surrounded by a
guard potential to suppress the effects of common-mode noise. The low voltage-current output LO
terminal is connected to the guard.
Appendix