Appendix
App-1
IM 2553A-01EN
3
2
1
4
5
6
7
8
9
10
11
12
13
14
App
Index
Appendix 1 Block Diagram
Pt100
HI
LO
Output
terminals
Resistance
source circuit
Power
amplifier
+V
−V
Range switching circuit
Guard
+
−
Pre-
amp
Reference
voltage
Vref
DAC
PWM
ADC
INT RJ sensor
measurement
circuit
• DAC control
• Range/feedback
switching control
• Resistance source
control circuit
• INT RJ sensor
measurement
+ DAC code
generation
Value
smoothing
Correction
value
calculation
Ground side
FPGA
To the CPU
Isolated side
Ground side
Isolated side
FPGA
Isolated power supply
When the output is turned on or when the source value is changed, a source code for setting the DAC
is sent from the CPU/FPGA on the ground side to the FPGA on the isolated side. To the source code,
the FPGA on the isolated side applies overshoot suppression and rising slope control (smoothing) for
reducing inrush current for when a capacitive load is connected. Then, the FPGA sends the source
code to the DAC.
On the other hand, the high-speed PWM ADC is sequentially measuring reference voltage Vref, the
zero level (circuit ground), and the output of its own DAC. The source code is compared and corrected
with these values and continuously transferred from the FPGA on the isolated side to the DAC. This
method provides stable DAC output.
The amplifier output is connected to the HI terminal side during voltage sourcing and LO terminal
during current sourcing. The pre-amp employs a low-noise, high-precision amplifier that accurately
amplifies the DAC output. The power amplifier employs a power-transistor-based push-pull-output
amplifier that enables sink operation.
The 2553A does not use relays to invert the polarity, so glitches due to polarity switching do not occur.
The isolated side is surrounded by a guard potential to suppress the effects of common-mode noise.
The guard is connected to the LO terminal.
Appendix
