5.9.2.6
Call OB 80 on cyclic interrupt error
Once during a cyclic interrupt OB (OB 28, 29, 32 ... 35) the same cyclic interrupt is
requested, the interrupt requests are collected and processed sequentially. Via the
parameter
‘OB 80 for cyclic interrupt’
you can set here for the corresponding cyclic inter-
rupt group that on a cyclic interrupt instead of the sequential processing the OB 80 is to
be called. With this parameter you have the following settings:
n
Deactivated (default)
–
At a cyclic interrupt error the interrupt requests are collected and processed
sequentially.
n
for OB...
–
At a cyclic interrupt error of the corresponding cyclic interrupt OB, the OB 80 is
called.
5.10 Project transfer
There are the following possibilities for project transfer into the CPU:
n
Transfer via MPI/PROFIBUS
n
Transfer via Ethernet
n
Transfer via Memory card
5.10.1
Transfer via MPI/PROFIBUS
For transfer via MPI/PROFIBUS the CPU has the following interface:
n
X2: MPI interface
n
X3: PROFIBUS interface
The structure of a MPI net is electrically identical with the structure of a PROFIBUS net.
This means the same rules are valid and you use the same components for the build-up.
The single participants are connected with each other via bus interface plugs and
PROFIBUS cables. Per default the MPI net runs with 187.5kbaud. VIPA CPUs are deliv-
ered with MPI address 2.
The MPI programming cables are available at VIPA in different variants. The cables pro-
vide a RS232 res. USB plug for the PC and a bus enabled RS485 plug for the CPU. Due
to the RS485 connection you may plug the MPI programming cables directly to an
already plugged plug on the RS485 jack. Every bus participant identifies itself at the bus
with an unique address, in the course of the address 0 is reserved for programming
devices.
A cable has to be terminated with its surge impedance. For this you switch on the termi-
nating resistor at the first and the last participant of a network or a segment. Please make
sure that the participants with the activated terminating resistors are always power sup-
plied. Otherwise it may cause interferences on the bus.
Overview
General
Net structure
MPI programming cable
Terminating resistor
VIPA System 300S
+
Deployment CPU 314-6CF23
Project transfer > Transfer via MPI/PROFIBUS
HB140 | CPU | 314-6CF23 | en | 19-01
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