OPQ Programmer’s Guide V 1.1
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4
Register structure
OPQ synthesizer has 256 8-bit registers, or at least 256 register addresses, not all have
any functionality. All registers are write-only, except register 00H, which is read-only.
One big difference to OPL3 is that all registers are directly addressable, because the chip
has 8 address lines. This makes writing and reading the registers simpler, no need for two-
phase operations.
The registers show up as 256 consecutive addresses in the controlling processor’s
address space. This may be memory address space or I/O address space, depending on
the hardware designer’s decisions. In PSR-70, registers are in memory address space,
because Z80 has only 256 register I/O address space, so the OPQ chip would alone eat
up the whole I/O address space.
4.1 Register address groups
High level classification of registers can be done by grouping the registers in groups of 32
registers. The register group number is the 3 most significant bits in the register address.
Register
group nr
Register
adresses
Group’s functionality
0
00H...1FH
General and channel specific settings
1
20H...3FH
Frequency settings
2
40H...5FH
Frequency multiplier/detune settings
3
60H...7FH
Output level settings
4
80H...9FH
Envelope: attack rate settings
5
A0H...BFH
Envelope: decay rate settings
6
C0H...DFH
Envelope: sustain rate settings
7
E0H...FFH
Envelope: sustain level/release rate settings
Table 2. Register groups
Register groups 0 and 1 need a bit more consideration, so lets look first at groups 2...7,
which are more straightforward.
4.2 Register groups 2...7
In register groups 2...7 all settings are operator specific, meaning there is a register for
each of the 32 operators and each operator may have different settings. The lower 5 bits
of the register address can be thought as the operator number (0...31) and it can be
mapped to channel number (0...7) and operator (Op0...Op3) using the table 1 on page 5.
