OPQ Programmer’s Guide V 1.1
4
state logic implemented in hardware, but to my understanding it is not used when
accessing the OPQ chip. This gives some rough idea about the bus timing specifications.
The chip comes in a 40-pin DIP package and the pinout is:
Pin functions:
VDD, VSS
5V supply
D7...D0
Data bus from/to CPU
A7...A0
Address bus from CPU
WR, RD
Write/read signals from CPU
CS, EN, EN
Chip select and enable signals from address decoding. In PSR-70
only CS is used, EN and EN are connected permanently active.
IRQ
Interrupt request to CPU
IC
Inital clear ( = reset) from reset logic
SO, RSH, LSH
Serial data out to DAC. In YM3012, signals SD, SAM1, SAM2
respectively.
ø10
Clock out to DAC
X1, X2
Crystal. In PSR-70, a 3.579 MHz is used.
