OPQ Programmer’s Guide V 1.1
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5
Register contents
Each register is 8 bits wide. They are described here by register groups.
All registers are write-only, the value written cannot be read back. Only exception is
register 00H, which is read-only.
Before writing to any register, software must check that BUSY-bit in register 00H is zero. At
least this is how the PSR-70 firmware does it, I have not tested what happens, if you don’t
obey this.
5.1 Register addresses 00H...0FH
This register area contains only few registers that actually do something. Most registers
seem not to affect anything.
5.1.1 Register 00H: Status register (read-only)
This is the only readable register. It returns status information. Following bits can be
inferred from the PSR-70 firmware:
D7
D6
D5
D4
D3
D2
D1
D0
BUSY
-
-
-
-
INT1
-
INT2
BUSY
OPQ is busy. Every time PSR-70 firmware wants to write to any
register, it first waits that this bit goes to 0.
INT1
OPQ interrupt is active. This bit is 1 when OPQ has set its IRQ-line
active.
INT2
Unknown. PSR-70 firmware tests for interrupt by masking register 00H
value with 05H, so also this bit could be counted as an active
interrupt. In my own tests I have never seen this bit active.
5.1.2 Register 03H: Timer control
This register controls the timer function. I have not figured out how the controlling is
actually done, but every time the interrupt occurs, PSR-70 firmware writes 71H to this
register. As a consequence, next interrupt occurs after 10 ms. I have copied this behavior
to my own test programs and it works. If I don’t write to this register, next interrupt will not
occur.
This is not a counter start value or compare value, because it does not behave like that. It
is possible to stop the interrupts coming by writing suitable values, but they don’t make
much sense. I have not found any way to control the interrupt interval.
