Yamaha Tyros3, Руководство по обслуживанию

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Tyros3
42
PIN
NO.
I/O FUNCTION NAME
PIN
NO.
I/O FUNCTION NAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DV
SS
DV
DD
MCLK
PDN
BICK
SDATA
LRCK
SMUTE/CSN
DFS0/CAD0
DEM0/CCLK
DEM1/CDTI
DIF0
DIF1
DIF2
-
-
I
I
I
I
I
I
I
I
I
I
I
I Digital ground
Digital power 3.3 V
Master clock input
Power-down mode
Audio serial data clock
Audio serial data input
L/R clock
Soft mute/Chip select
Sampling speed mode select/Chip address 0
De-emphasis enable 0/Control data clock
De-emphasis enable 1/Control data input
Digital input format
15
16
17
18
19
20
21
22
23
24
25
26
27
28 TTL
VREFL
VREFH
AV
DD
AV
SS
AOUTR-
AOUTR+
AOUTL-
AOUTL+
VCOM
P/S
TST1/DZFL
TST2/CAD1
ACKS/DZFR
I
I
I
-
-
O
O
O
O
O
I
O
I
I/O
CMOS/TTL level select
Low level voltage reference input
High level voltage reference input
Analog power 5 V
Analog ground
Rch negative analog output
Rch positive analog output
Lch negative analog output
Lch positive analog output
Common voltage output
Parallel/serial select
Test 1/Lch zero input detect
Test 2/Chip address 1
Master clock auto setting mode/Rch zero input detect
AK4396VF-E2 (X8324A00) DAC (Digital to Analog Converter)
DM: IC900, 901
PIN
NO.
I/O FUNCTION NAME
PIN
NO.
I/O FUNCTION NAME
DS99R103TSQX/NOPB (X9323A00) LVDS
DM: IC8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
DIN[23:0]
DIN[23:0]
DIN[23:0]
DIN[23:0]
DCAOFF
VssL
V
DD
L
DCBOFF
TPWDNB
TCLK
TRFB
VODSEL
RESRVD
V
DD
PT1
VssPT1
V
DD
PT0
VssPT0
DEN
I
I
I
I
I
I
I
I
I
I
I
I
Transmitter Parallel Interface Data Inputs Pins.
Tie LOW if unused.
RESERVED - This pin MUST be tied LOW.
Digital Ground, Tx Logic Ground
Digital Voltage supply, Tx Logic Power
RESERVED - This pin MUST be tied LOW.
Transmitter Power Down Bar
●
TPWDNB = H; Transmitter is Enabled and ON.
●
TPWDNB = L; Transmitter is in power down mode (Sleep),
LVDS Driver DOUT (+/-) Outputs are in TRI-STATE stand-by
mode, PLL is shutdown to minimize power consumption.
Transmitter Parallel Interface Clock Input Pin.
Strobe edge set by TRFB configuration pin
Transmitter Clock Edge Select Pin
●
TRFB = H; Parallel Interface Data is strobed on the Rising Clock Edge
●
TRFB = L; Parallel Interface Data is strobed on the Falling Clock Edge
VOD Level Select
●
VODSEL = L; LVDS Driver Output is ~400 mV (RL = 100 Ω )
●
VODSEL = H; LVDS Driver Output is ~800 mV (RL = 100
Ω
)
For normal applications, set this pin LOW. For long cable ap-
plications where a larger VOD is required, set this pin HIGH.
RESERVED - This pin MUST be tied LOW.
Analog Voltage supply, PLL Power
Analog Ground, PLL Ground
Analog Voltage supply, VCO Power
Analog Ground, VCO Ground
Transmitter Data Enable
●
DEN = H; LVDS Driver Outputs are Enabled (ON).
●
DEN = L; LVDS Driver Outputs are Disabled (OFF),
Transmitter LVDS Driver DOUT (+/-) Outputs are in TRI-
STATE, PLL still operational and locked to TCLK.
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
DOUT-
DOUT+
VssDR
V
DD
DR
PRE
Vss
DIN[23:0]
DIN[23:0]
DIN[23:0]
DIN[23:0]
DIN[23:0]
V
DD
T
VssT
DIN[23:0]
DIN[23:0]
DIN[23:0]
DIN[23:0]
DIN[23:0]
DIN[23:0]
DIN[23:0]
DIN[23:0]
DIN[23:0]
DIN[23:0]
V
DD
IT
VssIT
DIN[23:0]
DIN[23:0]
DIN[23:0]
DIN[23:0]
DIN[23:0]
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Transmitter LVDS Inverted (-) Output. This output is inten-
ded to be loaded with a 100 ohm load to the DOUT- pin.
Transmitter LVDS True (+) Output. This output is intend-
ed to be loaded with a 100 ohm load to the DOUT+ pin.
Analog Ground, LVDS Output Ground
Analog Voltage Supply, LVDS Output Power
PRE-emphasis select pin.
●
PRE = (RPRE
≧
3 k
Ω
); Imax = [(1.2/R) 20], Rmin = 3 k
Ω
●
PRE = H or floating; pre-emphasis is disabled
ESD Ground
Transmitter Parallel Interface Data Inputs Pins.
Tie LOW if unused.
Digital Voltage supply, Tx Serializer Power
Digital Ground, Tx Serializer Ground
Transmitter Parallel Interface Data Inputs Pins.
Tie LOW if unused.
Digital Voltage supply, Tx Input Power
Digital Ground, Tx Input Ground
Transmitter Parallel Interface Data Inputs Pins.
Tie LOW if unused.