Yamaha Tyros TRS-MS01, Руководство по обслуживанию

Страница: 27 / 153

27
Tyros / TRS-MS01
PIN PIN
NO.
NAME I/O FUNCTION
NO.
NAME I/O FUNCTION
1 MD1 I Mode control 105 CKE/PTK5 I/O CK enable / Port K
2 MD2 I 106 RAS3L/PTJ0 I/O RAS address bus / Port J
3 Vcc(RTC) - Power 1.8 V 107 PTJ1 I/O Port J
4 XTAL2 O Cry stal oscillator 108 CASL/PTJ2 I/O CAS address bus / Port J
5 EXTAL2 I 109 VssQ - Ground
6 Vss(RTC) - Ground 110 CASU/PTJ3 I/O CAS address bus / Port J
7 NMI I Non-maskable interrupt request 111 VccQ - Power 3.3 V
8 IRQ0/IRL0/PTH0 I 112 PTJ4 I/O
Port J
9 IRQ1/IRL1/PTH1 I 113 PTJ5 I/O
10 IRQ2/IRL2/PTH2 I Interrupt request / Port H 114 DACK0/PTD5 I/O
DMA acknowledge / Port D
11 IRQ3/IRL3/PTH3 I 115 DACK1/PTD7 I/O
12 IRQ4/PTH4 I 116 PTE6 I/O
Port E
13 D31/PTB7 I/O 117 PTE3 I/O
14 D30/PTB6 I/O 118 RAS3U/PTE2 I/O RAS address bus / Port E
15 D29/PTB5 I/O
Data bus / Port B
119 PTE1 I/O Port E
16 D28/PTB4 I/O 120 TDO/PTE0 I/O Test data / Port E
17 D27/PTB3 I/O 121 BACK O Bus acknowledge
18 D26/PTB2 I/O 122 BREQ I Bus request
19 VssQ - Ground 123 WAIT I Hardware wait request
20 D25/PTB1 I/O Data bus / Port B 124 RESETM I Manual reset
21 VccQ - Power 3.3 V 125 ADTRG/PTH5 I Analog trigger / Port H
22 D24/PTB0 I/O Data bus / Port B 126 IOIS16/PTG7 I Write protect / Port G
23 D23/PTA7 I/O 127 ASEMD0/PTG6 I ASE mode / Port G
24 D22/PTA6 I/O
Data bus / Port A
128 ASEBRKAK/PTG5 I/O ASE break acknowledge / Port G
25 D21/PTA5 I/O 129 PTG4/CKIO2 I/O Port G / Clock output
26 D20/PTA4 I/O 130 AUDATA3/PTG3 I/O
AUD data / Port G
27 Vss - Ground 131 AUDATA2/PTG2 I/O
28 D19/PTA3 I/O Data bus / Port A 132 Vss - Ground
29 Vcc - Power 1.8 V 133 AUDATA1/PTG1 I/O AUD data / Port G
30 D18/PTA2 I/O 134 Vcc - Power 1.8 V
31 D17/PTA1 I/O Data bus / Port A 135 AUDATA0/PTG0 I/O AUD data / Port G
32 D16/PTA0 I/O 136 TRST/PTF7/PINT15 I Test reset / Port F / Port interruption
33 VssQ - Ground 137 TMS/PTF6/PINT14 I Test mode switch / Port F / Port interruption
34 D15 I/O Data bus 138 TDI/PTF5/PINT13 I Test data / Port F / Port interruption
35 VccQ - Power 3.3 V 139 TCK/PTF4/PINT12 I Test clock / Port F / Port interruption
36 D14 I/O 140 IRLS3/PTF3/PINT11 I
37 D13 I/O 141 IRL2/PTF2/PINT10 I
Interrupt request / Port F / Port interruption
38 D12 I/O 142 IRLS1/PTF1/PINT9 I
39 D11 I/O 143 IRLS0/PTF0/PINT8 I
40 D10 I/O Data bus 144 MD0 I Mode control
41 D9 I/O 145 Vcc(PLL1) - Power 1.8 V
42 D8 I/O 146 CAP1 - Capacitor
43 D7 I/O 147 Vss(PLL1) - Ground
44 D6 I/O 148 Vss(PLL2) - Ground
45 VssQ - Ground 149 CAP2 - Capacitor
46 D5 I/O Data bus 150 VCC(PLL2) - Power 1.8 V
47 VccQ - Power 3.3 V 151 AUDCK/PTH6 I AUD clock / Port H
48 D4 I/O 152 Vss - Ground
49 D3 I/O 153 Vss -
50 D2 I/O Data bus 154 Vcc - Power 1.8 V
51 D1 I/O 155 XTAL1 O Crystal oscillator
52 D0 I/O 156 EXTAL1 I
53 A0 O 157 STATUS0/PTJ6 I/O
Processor status / Port J
54 A1 O
Address bus
158 STATUS1/PTJ7 I/O
55 A2 O 159 TCLK/PTH7 I/O Timer clock / Port H
56 A3 O 160 /IRQOUT O Interrupt request output
57 VssQ - Ground 161 VssQ - Ground
58 A4 O Address bus 162 CKIO I/O System clock input / output
59 VccQ - Power 3.3 V 163 VccQ - Power 3.3 V
60 A5 O 164 TXD0/SCPT0 O Data transmission / SCI port
61 A6 O 165 SCK0/SCPT1 I/O Serial clock / SCI port
62 A7 O 166 TXD1/SCPT2 O Data transmission / SCI port
63 A8 O 167 SCK1/SCPT3 I/O Serial clock / SCI port
64 A9 O Address bus 168 TXD2/SCPT4 O Data transmission / SCI port
65 A10 O 169 SCK2/SCPT5 I/O Serial clock / SCI port
66 A11 O 170 RTS2/SCPT6 I/O Transmit request / SCI port
67 A12 O 171 RXD0/SCPT0 I
Data reception / SCI port
68 A13 O 172 RXD1/SCPT2 I
69 VssQ - Ground 173 Vss - Ground
70 A14 O Address bus 174 RXD2/SCPT4 I Data reception / SCI port
71 VccQ - Power 3.3 V 175 Vcc - Power 1.8 V
72 A15 O 176 CTS2/IRQ5/SCPT7 I Transmit clear / Interrupt request / SCI port
73 A16 O 177 MCS7/PTC7/PINT7 I/O
74 A17 O 178 MCS6/PTC6/PINT6 I/O
Mask ROM chip select / Port C / Port interruption
75 A18 O Address bus 179 MCS5/PTC5/PINT5 I/O
76 A19 O 180 MCS4/PTC4/PINT4 I/O
77 A20 O 181 VssQ - Ground
78 A21 O 182 WAKEUP/PTD3 I/O Standby mode Interrupt request output / Port D
79 Vss - Ground 183 VccQ - Power 3.3 V
80 A22 O Address bus 184 RESETOUT/PTD2 I/O Reset output / Port D
81 Vcc - Power 1.8 V 185 MCS3/PTC3/PINT3 I/O
82 A23 O Address bus 186 MCS2/PTC2/PINT2 I/O
Mask ROM chip select / Port C / Port interruption
83 VssQ - Ground 187 MCS1/PTC1/PINT1 I/O
84 A24 O Address bus 188 MCS0/PTC0/PINT0 I/O
85 VccQ - Power 3.3 V 189 DRAK0/PTD1 I/O DMA acknowledge / Port D
86 A25 O Address bus 190 DRAK1/PTD0 I/O
87 BS/PTK4 I/O Bus cycle / Port K 191 DREQ0/PTD4 I
DMA request / Port D
88 RD O Read strobe 192 DREQ1/PTD6 I
89 WE0/DQMLL O Select signal (D7-D0) / D QM (SDRAM) 193 RESETP I Power on reset
90 WE1/DQMLU/WE O Select signal (D15-D8) / D QM (SDRAM) / Write enable 194 CA I Chip active
91 WE2/DQMUL/ICIORD/PTK6 I/O Select signal (D23-D16) / D QM (SDRAM) / I/O read / Port K 195 MD3 I
92 WE3/DQMUU/ISIOWR/PTK7 I/O Select signal (D31-D24) / D QM (SDRAM) / I/O write / Port K 196 MD4 I Mode control
93 RD/WR O Read / Write 197 MD5 I
94 AUDSYNC/PTE7 I/O AUD cycle / Port E 198 AVss - Analog ground
95 VssQ - Ground 199 AN0/PTL0 I
96 CS0/MCS0 O Chip select / Mask ROM chip select 200 AN1/PTL1 I
97 VccQ - Power 3.3V 201 AN2/PTL2 I
Analog input / Port L
98 CS2/PTK0 I/O 202 AN3/PTL3 I
99 CS3/PTK1 I/O Chip select / Port K 203 AN4/PTL4 I
100 CS4/PTK2 I/O 204 AN5/PTL5 I
101 CS5/CE1A/PTK3 I/O Chip select / Chip enable / Port K 205 AVcc - Analog power 3.3 V
102 CS6/CE1B O Chip select / Chip enable 206 AN6/DA1/PTL6 I/O Analog input / Analog output / Port L
103 CE2A/PTE4 I/O Chip enable / Port E 207 AN7/DA0/PTL7 I/O
104 CE2B/PTE5 I/O 208 AVss - Analog ground
HD6417709SF133 (X2081A00)
CPU (SH3)
DM: IC63