SVC110/SVC110S
11
■
IC BLOCK DIAGRAM
（IC ブロック図）
•
NJM3404AV
(XV410A00)
Dual operational amplifier
■
LSI PIN DESCRIPTION
（LSI端子機能表）
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
MD4
MD3
MD0
MD1
MD2
MCKO
XO
XI
ER0
ER1
ER2
REV0
REV1
REV2
MUTEN
ICN
PRG
MODE
VSS
AVSS
CVA
AORL
AORR
CHL
AIL
VDD
AIR
CHR
AOFL
AOFR
AVDD
CVB
External RAM interface data
Master clock output
Crystal oscillator connection
Crystal oscillator connection
Eary refrection preset select
Effect select
Mute
Initial clear
Program select
Preset mode (H=DC +5V)
Ground
Ground (analog)
ADC midpoint voltage
N.C.
N.C.
Sample hold capacitor connection
Lch ADC input
DC D+5V
Rch ADC input
Sample hold capacitor connection
Lch DAC output
Rch DAC output
DC A+5V
Rch midpoint voltage
I/O
I/O
I/O
I/O
I/O
O
O
I
I
I
I
I
I
I
I
I
I
I
-
-
-
O
O
I
I
-
I
I
O
O
-
I
PIN
No.
NAME
FUNCTION
I/O
PIN
No.
NAME
I/O
FUNCTION
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
AVDD
VDD
TST0
TST1
DOEN
SDO1
SDO0
WC
BCO
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA12
MA14
VSS
MA10
MA011
MA09
MA8
MA13
VDD
WEN
OEN
CEN
MD7
MD6
MD5
-
-
-
-
-
O
O
O
O
O
O
O
O
O
O
O
O
O
O
-
O
O
O
O
O
-
I
I
I
I/O
I/O
I/O
DC A+5V
DC D+5V
Test
Test
Test
N.C.
N.C.
N.C.
N.C
External RAM interface address
Ground
External RAM interface address
DC D+5V
Write enable
Output enable
Chip select
External RAM interface data
•
YSS234
(XN299A00)
Digital Sound Processor
1
2
3
4
-V
8
7
6
5
Output A
+V
Non-Inverting
Input A
-DC Voltage Supply
+DC Voltage
Supply
Output B
Inverting
Input B
Non-Inverting
Input B
Inverting
Input A
+
-
+
-
1
2
3
4
8
7
6
5
Output A
+V
Non-Inverting
Input A
GND
+DC Voltage
Supply
Output B
Inverting
Input B
Non-Inverting
Input B
Inverting
Input A
+
-
+
-
1
2
3
4
V-
8
7
6
5
Output 1
+Input 1
V+
Output 2
-Input 2
+Input 2
-Input 1
+
-
+
-
Lx
5
1
2
Vref Circuit
Phase Comp.
Buffer
PWM Controller
OSC
fosc Control
Chip Enable
V
LX
limiter
V
OUT
4
GND
CE
1
2
3
5
4
CE
NC
Lx
GND
V
OUT
