Yamaha RX-V675, Руководство по обслуживанию

Страница: 133 / 182

A
1
2
3
4
5
6
7
8
9
10
B C D E F G H I J K L M N
133
DIGITAL 7/8
RX-V675/HTR-6066/RX-A730/TSR-6750
★
All voltages are measured with a 10MΩ/V DC electronic voltmeter.
★
Components having special characteristics are marked ⚠ and must be replaced
with parts having specifications equal to those originally installed.
★
Schematic diagram is subject to change without notice.
ANALOG IN
FL/FR
SBL/SBR
SL/SR
C/SW
DIGITAL IN
1.2 5.0 3.3 3.3
N O T I C E
U . S . A
G
C A N A D A
E U R O P E
L
C H I N A
A U S T R A L I A
S I N G A P O R E
K O R E A
G E N E R A L
U
C
T
A
K
R
J A P A N
( m o d e l )
B B R I T I S H
J
S O U T H E U R O P E E
V T A I W A N
F R U S S I A N
P L A T I N A M E R I C A
S B R A Z I L
H T H A I
HDIG_DSD0A
TDI
DSP1_N_RST DSP1_N_CS DIR_N_RST DIR1_N_CS
HWCK_DSD2B
HBCK_DCLK
H P S D 0 _ D S D 0 B
H W C K _ D S D 2 B
A V 1 _ D
A V 4 _ D
A V 3 _ D
D S P _ M O S I
D S P _ S C K
D I R 1 _ N _ I N T
TMS N_TRST
HDMI_AUD_RTN
AUP_WCK AUP_BCK AUP_MCK
HMCK
A V 4 _ D
A V 3 _ D
A V 2 _ D
A V 1 _ D
TDO
DIR_SDO DIR_BCK DIR_WCK
D I R _ N _ R S T
D I R 1 _ N _ C S
D S P _ M I S O
A D _ L
A D _ R
A D _ L
A D _ R
D A _ B C K
NCPU_MCK NCPU_BCK NCPU_WCK NCPU_SDO
DSP1_N_INT DSP1_N_SPIRDY DSP_MISO DSP_MOSI DSP_SCK DIR1_N_INT MT_DA
D A _ M C K
DIR_MCK
H D I G _ D S D 0 A
H D M I _ A U D _ R T N
H B C K _ D C L K
H M C K
N C P U _ W C K
N C P U _ S D O
N C P U _ B C K
/EMRAS /EMCS0
EMBA0 EMBA1
EMA0 EMA1 EMA2 EMA3 EMA4 EMA5 EMA6 EMA7 EMA8 EMA9
EMA11 EMA10
/ E M C A S
/ E M W E
E M C K E
E M D Q M 0
DA_SD_SB DA_SD_SR
DA_SD_F AUP_SDO
DA_BCK
AUP_WCK AUP_BCK
DA_WCK
DSP1_MCK
AUP_MCK
D I R _ W C K
T M S
T D I
T C K
T D O
D S P 1 _ N _ R S T
MT_DA DSP1_N_INT DSP1_N_CS DSP1_N_SPIRDY DSP_MOSI DSP_MISO
HPSD1_DSD1A HPSD3_DSD2A HPSD0_DSD0B HPSD2_DSD1B
E M A 2
E M B A 0
E M A 1 0 E M A 8
E M D 1 4
E M D 1 5
/ E M C A S
E M D 8
E M D 9
E M D 1 0
E M A 3
E M D 5
E M D 1 1
E M A 9
/ E M R A S
E M D 3
E M D Q M 1
/ E M C S 0
E M D 6
E M D Q M 0
E M D 2
/ E M W E
E M D 4
E M D 1
E M C K E
E M D 7
E M D 0
E M D 1 2
E M D 1 3
E M A 0
E M A 1 1
E M A 5
E M B A 1
E M A 6
E M A 4
E M A 1
E M A 7
E M C L K
SFL_DO
SFL_DI
N _ T R S T
D I R _ B C K
D A _ S D _ S B
D A _ S D _ S R
D A _ S D _ C S W
D A _ S D _ F
AUP_SDO
DIR_MCK
TCK
NCPU_SPDIF
E M D 8
E M D 9
E M D 1 0
E M D 1 1
E M D 1 2
E M D 1 3
E M D 1 4
E M D 1 5
E M D 0
E M D 1
E M D 2
E M D 3
E M D 7
E M D 6
E M D 5
E M D 4
H D I G _ D S D 0 A
DSP1_MCK
D A _ W C K
SFL_CLK
H P S D 1 _ D S D 1 A
H P S D 2 _ D S D 1 B
H P S D 3 _ D S D 2 A
H W C K _ D S D 2 B
D I R _ S D O
DA_MCK
E M C L K
E M D Q M 1
DSP_SCK_A
Z A D C _ M C K 1
DA_SD_CSW
Z_SPDIF
DAC_FLT
D A C _ F L T
B T _ S P D I F
B T _ S P D I F
Z _ S P D I F
Z A D C _ M C K 1
ZADC_MCK2
A V 2 _ D
N C P U _ M C K
N C P U _ S P D I F
Z A D C _ M C K 2
Z A D C _ B C K
Z A D C _ W C K
Z A D C _ S D O
Z A D C _ S D O
Z A D C _ W C K
Z A D C _ B C K
SFL_N_CS
DSP_SCK_A
I C 9 2 1
D 8 0 Y K 1 1 3 C P T P 4 0 0
Y D 9 9 8 A 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
8 4
8 3
8 2
8 1
4 5
4 6
4 7
4 8
4 9
5 0
5 1
5 2
5 3
5 4
5 5
5 6
5 7
5 8
5 9
6 0
6 1
6 2
6 3
6 4
6 5
96 97 98 99
100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
1 3 6
1 3 7
1 3 8
1 3 9
1 4 0
1 4 1
1 4 2
1 4 3
1 4 4
1 4 5
1 4 6
1 4 7
1 4 8
1 4 9
1 5 0
1 5 1
1 5 2
1 5 3
1 5 4
1 5 5
1 5 6
1 5 7
1 5 8
1 5 9
1 6 0
26 27 28 29 30 31
6 6
6 7
6 8
6 9
7 0
7 1
7 2
1 6 1
1 6 2
1 6 3
1 6 4
1 3 3
1 3 4
1 3 5
32
89 90 91 92 93 94 95
33 34 35 36 37 38 39 40
7 3
7 4
7 5
7 6
7 7
7 8
7 9
8 0
121 122 123 124 125 126 127 128
1 6 5
1 6 6
1 6 7
1 6 8
1 6 9
1 7 0
1 7 1
1 7 2
41 42 43 44
8 5
8 6
8 7
8 8 129 130 131 132
1 7 3
1 7 4
1 7 5
1 7 6
R 9 2 5 2
1 0 0 K
HPSD1_DSD1A
R9216
33
DSP1_N_CS
HDIG_DSD0A
0
J 9 2 0 5
C 9 3 0 9
n o _ u s e
C 9 2 6 1
0 . 1 / 1 0 ( B J )
C 9 2 7 5
1 0 / 6 . 3
C 9 3 1 5
0 . 0 1 / 1 6 ( B )
R9202
no_use
C B 9 2 4
n o _ u s e
C9264
0.1/10(BJ)
R 1 1 7 2 H 1 2 1 D - T 1 - F
X 9 2 9 2 A 0
I C 9 2 9
1
CEorCE
2
GND
3
NC
4
VDD
5
VOUT
R 9 2 2 0
1 0 0
D G N D
C9262
0.1/10(BJ)
R9224
33
R9296
no_use
C 9 2 2 2 0 . 1 / 1 0 ( B J )
C 9 3 1 0
n o _ u s e
R9276
100
C9278
4700P/25(B)
+ 5 . 5 V
C9237
0.1/10(BJ)
C 9 2 6 9
8 2 0 P / 1 6
R9241
47X4
R9218 10K
C9202
10/6.3
L 9 2 0 9
B K P 1 0 0 5 H S 6 8 0 - T
C 9 2 6 5
0 . 1 / 1 0 ( B J )
A G N D
R9278
33
+3.3DSP1
R 9 2 5 1
1 0 0 K
+ 1 . 2 D S P 1
C9242
0.1/10(BJ)
D G N D
R9214
33
DSP_SCK
C9284
10/6.3
HBCK_DCLK
C9236
0.1/10(BJ)
R 9 2 2 7
4 . 7 K
DGND
R 9 3 0 3
4 7 X 4
+ 3 . 3 D S P 1
C9238
0.1/10(BJ)
C 9 2 9 3
0 . 1 / 1 0 ( B J )
C 9 2 5 4
4 7 0 0 P / 2 5 ( B )
X L 9 2 2
2 0 M H Z
1
23
4
D G N D
C 9 2 4 3
0 . 1 / 1 0 ( B J )
R9239
47X4
I C 9 3 8
n o _ u s e
2
1
4
C 9 3 0 5
n o _ u s e
C 9 3 0 8
n o _ u s e
C9207
10/6.3
R9201
1M
R A L 0 3 5 P 0 1
Q 9 2 0 1
1 2 3
4 5 6
+ 3 . 3 D R 1
C 9 3 1 6
0 . 0 1 / 1 6 ( B )
D A _ B C K
+ 1 . 2 D S P 1
D G N D
C 9 2 5 8
0 . 1 / 1 0 ( B J )
HDMI_AUD_RTN
C9274
15P(CH)
HPSD0_DSD0B
C9256
0.1/10(BJ)
DSP_MOSI
+ 5 A
C9288
1/25
D A _ S D _ C S W
C9233
0.1/10(BJ)
C9294
no_use
C9271
470P(B)
C9203
10/6.3
R 9 2 4 2
n o _ u s e
C 9 2 2 7
0 . 1 / 1 0 ( B J )
D A _ S D _ S B
C 9 3 0 0
n o _ u s e
C9204
10/6.3
C9229
0.1/10(BJ)
+ 5 . 5 V
C9209
no_use
NCPU_SDO
L9201
BLM21PG600SN1D
A G N D
C9257
0.1/10(BJ)
DSP1_N_SPIRDY
Q 9 2 0 2
D T A 0 4 4 E U B T L
3
1
2
A V 1 _ D
C9289
1/25
R9237
47X4
C 9 2 9 8
n o _ u s e
R 9 2 2 5
4 . 7 K
R 9 2 0 0 4 7
D G N D
R P 1 3 0 Q 3 3 1 D - T R - F
Y C 2 8 8 A 0
I C 9 3 0
4
VDD
2
GND
3
VOUT
1
CE/CE
R 9 2 8 7
3 3
R 9 3 0 4
4 7 X 4
R9210
33
C9211
0.1/10(BJ)
R 9 2 2 6
4 . 7 K
R 9 3 0 5
4 7 X 4
L 9 2 0 4
B K P 1 0 0 5 H S 6 8 0 - T
D G N D
HPSD3_DSD2A
R 9 3 0 0
1 0 0
NCPU_SPDIF
R9223 10K
+ 3 . 3 D S P 1
A D _ R
C9232
0.1/10(BJ)
R 9 2 1 9
1 0 K
R 9 2 1 7
1 0 K
D G N D
D G N D
C9250
0.1/10(BJ)
DIR1_N_CS
R9213
33
R 9 2 2 8
4 . 7 K
AUP_SDO
C 9 2 6 6
0 . 0 1 / 1 6 ( B )
R P 1 3 0 Q 5 0 1 D - T R - F
Y C 2 8 9 A 0
I C 9 3 1
4
VDD
2
GND
3
VOUT
1
CE/CE
R 9 2 2 1
1 0 0
C9277
no_use
DSP1_N_RST
C9286
1/25
R9203
no_use
AUP_MCK
A V 4 _ D
C 9 2 4 6
0 . 1 / 1 0 ( B J )
A G N D
0
J9209
+ 1 . 2 D S P 1
D A _ M C K
MT_DA
C9302
no_use
C 9 2 9 1
0 . 1 / 1 0 ( B J )
C 9 2 6 8
0 . 1 / 1 0 ( B J )
C 9 2 2 0
0 . 1 / 1 0 ( B J )
R9297 4.7K
R9204
4.7K
D 8 . 1 +
C9255
4700P/25(B)
C 9 2 7 0
8 2 0 P / 1 6
+ 3 . 3 D S P 1
A V 2 _ D
HWCK_DSD2B
L 9 2 0 7
B K P 1 0 0 5 H S 6 8 0 - T
D G N D
DGND
DGND
C9285
10/6.3
R9211
100
C 9 3 1 3
n o _ u s e
C 9 2 4 4
0 . 1 / 1 0 ( B J )
D G N D
DSP1_N_INT
C 9 3 1 7
0 . 0 1 / 1 6 ( B )
C9272
10/6.3
D G N D
R927
7
33
HPSD2_DSD1B
C 9 2 2 6
0 . 1 / 1 0 ( B J )
IC938
V +
5
C 9 2 2 4
0 . 1 / 1 0 ( B J )
R9238
47X4
C9253
10/16
+ 3 . 3 D S P
C 9 2 1 9
0 . 1 / 1 0 ( B J )
C9295
470P(B)
DIR_N_RST
C9235
0.1/10(BJ)
HMCK
C 9 2 9 7
n o _ u s e
C 9 2 4 7
0 . 1 / 1 0 ( B J )
R9212
33
C 9 3 0 3
n o _ u s e
C 9 2 9 2
0 . 1 / 1 0 ( B J )
C9231
0.1/10(BJ)
C 9 2 7 9
0 . 1 / 1 0 ( B J )
IC938 V- 3
D G N D
D G N D
C921
2
10/16
D G N D
C 9 3 0 1
n o _ u s e
R 9 2 3 1 4 7
IC924
PCM9211PTR
YD216A0
1
E R R O R / I N T 0
2
N P C M / I N T 1
3
M P I O _ A 0
4
M P I O _ A 1
5
M P I O _ A 2
6
M P I O _ A 3
7
M P I O _ C 0
8
M P I O _ C 1
9
M P I O _ C 2
10
M P I O _ C 3
11
M P I O _ B 0
12
M P I O _ B 1
13
MPIO_B
2
14
MPIO_B
3
15
MPO0
16
MPO1
17
DOUT
18
LRCK
19
BCK
20
SCKO
21
DGND
22
DVDD
23
MDO/ADR0
24
MDI/SDA
25
M C / S C L
26
M S / A D R 1
27
M O D E
28
R X I N 7 / A D I N 0
29
R X I N 6 / A L R C K I 0
30
R X I N 5 / A B C K I 0
31
R X I N 4 / A S C K I 0
32
R X I N 3
33
R X I N 2
34
R S T
3
5
R X I N 1
36
V D D R X
37
RXIN
0
38
GNDR
X
39
XT
I
40
XT
O
41
AGND
42
VCC
43
FILT
44
VCO
M
45
AGNDA
D
46
VCCA
D
47
VIN
L
48
VINR
C 9 2 9 0
0 . 1 / 1 0 ( B J )
C 9 2 1 6
0 . 1 / 1 0 ( B J )
C 9 3 1 2
n o _ u s e
C9263
0.1/10(BJ)
R9288
10K
C9287
1/25
C9239
0.1/10(BJ)
C9251
0.1/10(BJ)
C9206 10/6.3
C9241
0.1/10(BJ)
C 9 2 4 8
0 . 1 / 1 0 ( B J )
A V 3 _ D
C 9 2 8 1
0 . 1 / 1 0 ( B J )
C9213
0.1/10(BJ)
R9206
33
D G N D
C 9 2 0 5
1 0 / 6 . 3
C 9 2 2 1
0 . 1 / 1 0 ( B J )
R 9 2 3 2
4 7 X 4
R9279
680
+ 3 . 3 D R 1
D A _ S D _ F
+ 3 . 3 D R 1
C9230
0.1/10(BJ)
A D _ L
C 9 3 0 7
n o _ u s e
R9209
33
C 9 2 1 7
0 . 0 1 / 1 6 ( B )
C9234
0.1/10(BJ)
NCPU_MCK
+ 3 . 3 D S P
DSP_MISO
D G N D
C9240
0.1/10(BJ)
R 9 2 7 3
1 0 K
R9207
33
L 9 2 0 5
B K P 1 0 0 5 H S 6 8 0 - T
C9276
0.068/25
+ 3 . 3 D S P
DSP_PON
D A _ W C K
R 9 2 7 4
3 3
C9252
10/16
R9222
33
C9228
0.1/10(BJ)
NCPU_BCK
L 9 2 0 8
B K P 1 0 0 5 H S 6 8 0 - T
DGND
C 9 2 6 0
0 . 1 / 1 0 ( B J )
+ 3 . 3 D S P
D G N D
C 9 2 1 0
4 7 0 0 P / 2 5 ( B )
R 9 3 0 2
4 7 X 4
C 9 2 1 8
0 . 1 / 1 0 ( B J )
C 9 2 8 2
0 . 1 / 1 0 ( B J )
M12L64164A-5TG2
X9625C0
IC922
1
V C C
2
D Q 0
3
V C C Q
4
D Q 1
5
D Q 2
6
V S S Q
7
D Q 3
8
D Q 4
9
V C C Q
10
D Q 5
11
D Q 6
12
V S S Q
13
D Q 7
14
V C C
15
D Q M L
16
W E
17
C A S
18
R A S
19
C S
20
A 1 3 / B A 0
21
A 1 2 / B A 1
22
A 1 0 / A P
23
A 0
24
A 1
31
A 6
32
A 7
33
A 8
34
A 9
35
A 1 1
36
N C
37
C K E
38
C L K
39
D Q M U
40
N C
41
V S S
42
D Q 8
43
V C C Q
44
D Q 9
45
D Q 1 0
46
V S S Q
47
D Q 1 1
48
D Q 1 2
49
V C C Q
50
D Q 1 3
51
D Q 1 4
52
V S S Q
53
D Q 1 5
54
V S S
25
A 2
27
V C C
28
V S S
30
A 5
26
A 3
29
A 4
C 9 2 4 9
0 . 1 / 1 0 ( B J )
C 9 3 0 6
n o _ u s e
C 9 2 4 5
0 . 1 / 1 0 ( B J )
C 9 2 5 9
0 . 1 / 1 0 ( B J )
R9208
33
X L 9 2 1
2 4 . 5 7 6 M H Z
4
1 2
3
R9205
33
C9201
10/6.3
NCPU_WCK
AUP_WCK
R928
1
33
+ 3 . 3 D
C 9 2 2 5
0 . 1 / 1 0 ( B J )
DIR1_N_INT
C9299 no_use
AUP_BCK
R 9 2 8 6
3 3
D G N D
C 9 3 0 4
n o _ u s e
L 9 2 0 3
B K P 1 0 0 5 H S 6 8 0 - T
R9230 150X4
C 9 2 0 8
n o _ u s e
D A _ S D _ S R
0
J 9 2 1 0
C 9 2 2 3 0 . 1 / 1 0 ( B J )
C 9 2 9 6
1 0 0 0 P ( B )
R9243
33
R9240
47X4
+ 1 . 2 D S P 1
L9202
BKP1005HS680-T
C 9 2 6 7
0 . 1 / 1 0 ( B J )
0
J9201
+ 3 . 3 D R 1
C 9 2 1 4
1 8 P ( C H )
C 9 2 1 5
1 8 P ( C H )
C9273
12P(CH)
R9275
680
IC923
W25Q80BVSSIG
Y F 2 7 1 A 0
1
/CS
2
D0
3
/WP
4
GND
5
DI
6
CLK
7
/HOLD
8
VCC
R 9 2 2 9 3 3
V -
3
R 9 2 9 3
3 3
C9318
0.1/10(BJ)
D G N D
C9280
0.1/10(BJ)
IC927
V +
5
R 9 2 9 4
3 3
+ 3 . 3 D S P
I C 9 2 6
T C 7 S H 3 2 F U
2
1
4
V -
3
I C 9 2 7
T C 7 S H 3 2 F U
2
1
4
C9283
0.1/10(BJ)
IC926
V +
5
L9206
BKP1005HS680-T
DSP_SCK_A
P S D 5 + 1 R D 3 . 3 +
Z A D C _ M C K 1
R 9 2 1 5
3 3
Z_SPDIF
R 9 2 3 3
n o _ u s e
R9234
100
D A C _ F L T
B T _ S P D I F
R 9 2 3 5
n o _ u s e
R 9 2 8 9
1 0 0 K
Z A D C _ B C K
Z A D C _ W C K
Z A D C _ S D O
R 9 2 3 6
1 0 0 K X 4
D G N D
R 9 2 4 4
n o _ u s e
R 9 2 4 5
n o _ u s e
R9246
no_use
R 9 2 4 7
n o _ u s e
I C 9 3 2
n o _ u s e
1
ADJ
2
GND
3
CE
4
VDD
5
VOUT
R9248
no_use
R9249
no_use
+ 3 . 3 D
D G N D
C9314
no_use
C9311
no_use
J 9 2 1 1
n o _ u s e
R9250
no_use
R9272
2.4K
R9268
2.4K
R 9 2 7 1
1 . 8 K
R 9 2 6 9
1 . 8 K
S h e e t 7 : D S P / D I R
DGND
PD(+3.3V)
t o 0 0 4 . s h t ( H D M I T x )
KEY
t o 0 0 5 . s h t
( u - C o m )
TDI TCK TDO
DGND
N_TRST
TMS
TCK_RET
DGND DGND
+ 1 . 2 D S P 1 + 3 . 3 D R 1 + 5 D S P + 3 . 3 D S P
t o 0 0 6 . s h t
( N e t / U S B )
V c e h = 1 ~ 6 . 5 V
V c e l = 0 - 0 . 4 V V c e h = 1 ~ 6 V
V c e l = 0 - 0 . 4 V V c e h = 1 ~ 6 . 5 V
V c e l = 0 - 0 . 4 V
S R L / S R R
to 008.sht (Power)
C / S W
F L / F R
S B L / S B R
V 6 7 5 - A 8 3 0 : 2 . 4 V r m s t o 3 V p p
R 9 2 6 8 , 9 2 7 2 = 2 . 4 k
R 9 2 6 9 , 9 2 7 1 = 2 . 4 k
to 008.sht (Power)
( Z 2 _ A D L )
( Z 2 _ A D R )
I C / C B / X L : 9 2 1 - 9 3 9
O H T E R : 9 2 0 1 - 9 3 9 9
S E R I A L F L A S H B O O T
AXR1[0]
UART0_RXD UART0_TXD
AXR1[10] AXR1[11]
SPI1_ENA
SPI1_SCS[0] SPI0_SCS[0]
SPI0_CLK SPI0_ENA
SPI1_SOMI[0] SPI1_SIMO[0]
SPI1_CLK
SPI0_SOMI[0] SPI0_SIMO[0]
UHPI_HRDY
GP2[6]
EMA_OE
GP2[5]
EMA_BA[0] EMA_BA[1] EMA_A[10]
EMA_A[0] EMA_A[1] EMA_A[2] EMA_A[3] EMA_A[4] EMA_A[5] EMA_A[6] EMA_A[7] EMA_A[8] EMA_A[9]
EMA_A[11] EMA_A[12]
EMA_D[0]
E M A _ D [ 1 ]
E M A _ D [ 2 ]
D V D D
E M A _ D [ 3 ]
E M A _ D [ 4 ]
C V D D
E M A _ D [ 5 ]
E M A _ D [ 6 ]
D V D D
E M A _ D [ 7 ]
E M A _ W E
C V D D
E M B _ C A S
D V D D
E M B _ W E
E M B _ W E _ D Q M [ 0 ]
C V D D
E M B _ D [ 7 ]
E M B _ D [ 6 ]
E M B _ D [ 5 ]
D V D D
E M B _ D [ 4 ]
C V D D
E M B _ D [ 3 ]
C V D D
E M B _ D [ 2 ]
D V D D
E M B _ D [ 1 ]
E M B _ D [ 0 ]
E M B _ D [ 1 5 ]
D V D D
E M B _ D [ 1 4 ]
C V D D
E M B _ D [ 1 3 ]
E M B _ D [ 1 2 ]
E M B _ D [ 1 1 ]
D V D D
E M B _ D [ 1 0 ]
E M B _ D [ 9 ] /
E M B _ D [ 8 ]
E M B _ W E _ D Q M [ 1 ]
E M B _ C L K
D V D D
E M B _ S D C K E
EMB_A[12] DVDD EMB_A[11] EMB_A[9] CVDD EMB_A[8] EMB_A[7] EMB_A[6] EMB_A[5] EMB_A[4] DVDD EMB_A[3] EMB_A[2] EMB_A[1] EMB_A[0] CVDD EMB_A[10] EMB_BA[1] EMB_BA[0] EMB_CS[0] DVDD EMB_RAS AXR0[0] AXR0[1] AXR0[2] CVDD AXR0[3] AXR0[4] AXR0[5] AXR0[6] DVDD AXR0[7] AXR0[8] AXR0[9] AXR0[10] AXR0[11] AHCLKX0 ACLKX0 AFSX0 DVDD AHCLKR0 ACLKR0 AFSR0 AMUTE1
U S B 0 _ V D D A 1 2
U S B 0 _ V D D A 1 8
N C
U S B 0 _ D P
U S B 0 _ D M
N C
U S B 0 _ V D D A 3 3
P L L 0 _ V D D A
P L L 0 _ V S S A
O S C I N
O S C V S S
O S C O U T
R E S E T
C V D D
R T C _ X I
R T C _ C V D D
T R S T
D V D D
T M S
T D I
C V D D
T C K
T D O
D V D D
G P 7 [ 1 4 ]
C V D D
A H C L K X 1
C V D D
A C L K X 1
A F S X 1
D V D D
A C L K R 1
A F S R 1
C V D D
A X R 1 [ 8 ]
A X R 1 [ 7 ]
A X R 1 [ 6 ]
A X R 1 [ 5 ]
D V D D
A X R 1 [ 4 ]
A X R 1 [ 3 ]
A X R 1 [ 2 ]
A X R 1 [ 1 ]
R S V 2
DVDD CVDD CVDD CVDD CVDD DVDD DVDD DVDD DVDD
(2125)
X Z 4 1 4 F 0
X 9 6 2 5 C 0
P a r t N o . P a r t T y p e V e n d e r
W I N B O N D W 9 8 6 4 G 6 J H - 6
I C 9 2 2
E S M T M 1 2 L 6 4 1 6 4 A - 5 T G 2 M
6 4 M b i t
8 M b i t
M X I C M X 2 5 L 8 0 3 5 E M 2 I - 1 0 G
W 2 5 Q 8 0 B V S S I G
I C 9 2 3 B l a n k
V e n d e r
Y D 7 6 2 A 0
P a r t N o .
W I N B O N D
Y E 0 5 8 A 0
P a r t T y p e
E O N E N 2 5 Q 8 0 A - 1 0 0 H I P Y E 0 0 5 A 0
S D R A M
S e r i a l F l a s h M e m o r y
Y D 4 8 7 A 0 Z E N T E L A 3 V 6 4 S 4 0 E T P - G 6
(0.5%)
(0.5%)
( 0 . 5 % ) ( 0 . 5 % )
T P
A
1 s t M P
Y E 2 0 0 B 0 E M S T F 2 5 L 0 8 Q A - 1 0 0 P A G 2 S
T P
A
( 2 1 2 5 )
REMARKS
CAPACITOR
PARTS NAME
NO
NO
MARK
MARK
ELECTROLYTIC CAPACITOR
CERAMIC CAPACITOR
POLYESTER FILM CAPACITOR
POLYSTYRENE FILM CAPACITOR
MICA CAPACITOR
POLYPROPYLENE FILM CAPACITOR
SEMICONDUCTIVE CERAMIC CAPACITOR
P
TANTALUM CAPACITOR
TUBULAR
S
CAPACITOR CERAMIC
FILM SULFIDE POLYPHENYLENE
CAPACITOR
RESISTOR
REMARKS
NO MARK
PARTS NAME
CARBON
CARBON
METAL
METAL
METAL
FIRE
CEMENT
SEMI
FILM RESISTOR
FILM RESISTOR
OXIDE FILM RESISTOR
FILM RESISTOR
PLATE RESISTOR
PROOF CARBON FILM RESISTOR
MOLDED RESISTOR
VARIABLE RESISTOR
(P=5)
(P=10)
CHIP RESISTOR
VDD
A3
A2
A1
A0
A10/AP
A12
A13
CS
RAS
CAS
WE
LDQM
VDD
VSSQ
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
VDDQ
VDDQ
VSSQ
DQ0
VDD
VSS
A4
A5
A6
A7
A8
A9
A11
NC
CKE
CLK
UDQM
NC
VSS
VDDQ
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
VSSQ
VSSQ
VDDQ
DQ15
VSS
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
IC922 : M12L64164A-5TG
1M x 16-bit x 4 banks synchronous DRAM
CLK
CS
RAS
CAS
WE
C
o
mmand Decoder
C
ontr
ol Logic
Latch Cir
cuit
Input and Output
Buf
fe
r
R
o
w Decoder
Bank A
Sense Amplifier
Column Decoder
Data Control Circuit
L(U)DQM
DQ
CKE
Address
Clock
Generator
Row
Address
Buffer
Column
Address
Buffer
and
and
Refresh
Counter
Refresh
Counter
Mode
Register
Bank B
Bank C
Bank D
IC924 : PCM9211PTR
216-kHz digital audio interface transceiver (DIX) with stereo ADC and routing
PLL
DIT
MPO0/1
SELECTOR
MPIO_B
SELECTOR
MAIN
OUTPUT
PORT
ADC
Com. Supply
AUXIN1
ADC Standalone
ADC Mode
Control
MPIO_C
SELECTOR
OSC
SPI/I 2 C
INTERFACE
Reset and
Mode
Set
Divider
XMCKO
Divider
GPIO/GPO
Data
ADC
ANALOG
DIR
ANALOG
DIR
ANALOG
ALL
Function
Control
DIT CS
(48-bit)
DIR CS
(48-bit)
DIR
Interrupt
DIR
PC
and
PD
All Port
IS Calculator
Is Calculator
DIR
IS Calculator
MPIO_A
MPIO_B
MPIO_C
MPO1
MPO0
REGISTER
POWER SUPPLY
XMCKO
(To MPIO_A and MPO0/1)
SBCK/SLRCK
(To MPIO_A)
Secondary SCK/LRCK
EXTRA DIR FUNCTIONS
Divider
Selector
ERROR DETECTION
Flags
Validity Flag
User Data
BFRAME Detection
Channel Status Data
Interrupt System
Non PCM DETECTION
DTS-CD/LD Detection
ADC Clock
(SCK/BCK/LRCK)
DIR
ADC
DITOUT
RECOUT1
AUXOUT
AUXIN2
RECOUT0
AUTO
DIR
ADC
DOUT
RXIN7
SCKO/BCK/LRCK
AUXIN0
AUXIN1
AUXIN2
Clock/Data
Recovery
Lock
Detection
Lock:DIR
Unlock:ADC
33
35
32
31
30
29
28
3
4
5
6
37
RXIN0
RXIN0
RXIN1
RXIN2
RXIN3
RXIN4
RXIN5
RXIN6
RXIN7
RXIN8
RXIN9
RXIN10
RXIN11 RECOUT0
RECOUT1 DITOUT
RXIN1
RXIN2
RXIN3
RXIN4/ASCKIO
RXIN5/ABCKIO
RXIN6/ALRCKIO
FILT
RXIN7/ADIN0
AUXIN0
MPIO_A0
MPIO_A1
MPIO_A2
MPIO_A3
SCKO
BCK
LRCK
DOUT
MPO0
MPO1
MPIO_B0
MPIO_B1
MPIO_B2
MPIO_B3
48
47
44
VINL
VINR
VCOM
7
8
9
10
MPIO_C0
MPIO_C1
MPIO_C2
MPIO_C3
39
40
25
24
34
27
46
23
26
XTI
XTO
MS/ADR1
MDO/ADR0
MC/SCL
MDI/SDA
RST
MODE
VCCAD AGNDAD VCC DVDD AGND DGND VDDRX
MPIO_A
SELECTOR
43
AUTO
DIR
ADC
AUXIN0
AUXIN1
AUXIN2
AUTO
DIR
ADC
AUXIN0
AUXIN1
AUXIN2
20
19
18
17
15
11
12
13
14
ERROR/INT0
NPCM/INT1
1
2
16
45 22
GNDRX
38 21 42 41 36
V
DD
CE
Pin No.
1
2
3
4
5
Symbol
V
OUT
GND
CE
NC
V
DD
Description
Output Pin of Voltage Regulator
Ground Pin
Chip Enable Pin
No Connection
Input Pin
Vref
5 4
2 1
Current Limit
V
OUT
GND
IC929 : R1172H121D-T1-F
CMOS-based positive-voltage regulator IC
V
DD
CE
Vref
4 3
1 2
Current Limit
V
OUT
GND
Pin No.
1
2
3
4
Symbol
V
OUT
GND
CE
V
DD
Description
Output Pin
Ground Pin
Chip Enable ("H" Active)
Input Pin
IC930 : RP130Q331D-TR-F
Voltage regulator
V
DD
CE
Vref
4 3
1 2
Current Limit
V
OUT
GND
Pin No.
1
2
3
4
Symbol
V
OUT
GND
CE
V
DD
Description
Output Pin
Ground Pin
Chip Enable ("H" Active)
Input Pin
IC931 : RP130Q501D-TR-F
Voltage regulator
A
H
L
H
L
H
L
L
H H
H
H
L
B Y
1
3
2
5
4
GND
V
CC
IC926, 927 : TC7SH32FU
2-input OR gate
IN A
IN B
OUT Y
IC923 : W25Q80BVSSIG
8 M-bit flash memory with dual and quad SPI
Block Segmentation
xxFF00h
xxF000h
∙
xxFFFFh
xxF0FFh
∙
xx2F00h
xx2000h
∙
xx2FFFh
xx20FFh
∙
xx0F00h
xx0000h
∙
xx0FFFh
xx00FFh
Write Control
Logic
/WP(IO
2
)
∙
xx1F00h
xx1000h
∙
xx1FFFh
xx10FFh
∙
xxDF00h
xxD000h
Sector 15 (4KB)
Sector 14 (4KB)
Sector 13 (4KB)
Sector 2 (4KB)
Sector 1 (4KB)
Sector 0 (4KB)
∙
∙
∙
∙
xxDFFFh
xxD0FFh
∙
xxEF00h
xxE000h
∙
xxEFFFh
xxE0FFh
∙
0FFF00h
0F0000h
∙
0FFFFFh
003000h 0030FFh
002000h 0020FFh
001000h 0010FFh
000000h 0000FFh
0F00FFh
∙
Block 15 (64KB)
Security Register 3 - 0
∙
∙
∙
∙
∙
∙
08FF00h
080000h
∙
08FFFFh
0800FFh
∙
Block 8 (64KB)
07FF00h
070000h
∙
07FFFFh
0700FFh
∙
Block 7 (64KB)
00FF00h
000000h
∙
00FFFFh
0000FFh
∙
Block 0 (64KB)
Write Protect Logic and Row Decode
Status
Register
High Voltage
Generators
Page Address
Latch / Counter
Byte Address
Latch / Counter
Column Decode
And 256-Byte page Buffer
Beginning
Page Address
Data
Ending
Page Address
SPI
Command
and
Control Logic
/HOLD(IO 3 )
CLK
/CS
DI(IO
0
)
DO(IO
1
)
7
6
1
5
2
3
W25Q80BV
IC921: D80YK113CPTP400
Digital signal processor
PLL/Clock
Generator
w/OSC
Memory Protection
I/O Protection
C674x
TM
DSP MICRO-
PROCESSOR
Power/Sleep
Controller
Pin
Multiplexing
RTC/
32-KHz
OSC
GPIO
EDMA3
DMA Serial Interface
External Memory Interface
Control Timers
Connectivity
Shared Memory
Audio Ports
dMAX
System Control
Peripherals
Input
Clock(s)
JTAG Interface
Switched Control Resource (SCR)
DSP Subsystem
AET
256 KB L2 RAM
32 KB
L1 Pgm
32 KB
L1 RAM
1024 KB L2 ROM
128 KB
RAM
General-
Purpose
Timer
General-
Purpose
Timer
(Watchdog)
McASP
w/FIFO
UART I
2
C SPI
eHRPWM eQEP
HPI
USB2.0
OTG Ctlr
PHY
MMC/SD
(8b)
EMIFA(8b/16b)
NAND/Flash
16b SDRAM
EMIFB
SDRAM Only
(16b/32b)
eCAP
to DIGITAL 6/8
to DIGITAL 8/8
to DIGITAL 5/8
to DIGITAL 8/8
to DIGITAL 4/8
DIGITAL (1)
DSP
SDRAM
SERIAL
FLASH
DIR
No replacement part available.
RX-A730
RX-V675/HTR-6066/TSR-6750