A
1
2
3
4
5
6
7
8
9
10
B
C
D
E
F
G
H
I
J
K
L
M
N
73
DIGITAL 1/3
R-N602
SCHEMATIC DIAGRAMS
★
All voltages are measured with a 10MΩ/V DC electronic voltmeter.
★
Components having special characteristics are marked
⚠
and must be replaced
with parts having specifications equal to those originally installed.
★
Schematic diagram is subject to change without notice.
● 電圧は、内部抵抗 10MΩの電圧計で測定したものです。
● ⚠印のある部品は、安全性確保部品を示しています。部品の交換が必要な場合、
パーツリストに記載されている部品を使用してください。
● 本回路図は標準回路図です。改良のため予告なく変更することがあります。
3.3
3.3
5.5
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.2
3.3
3.3
0
0
0
3.3
0
0
2.9
(2.7)
2.6
2.6
5.5
0
0
3.3
3.3
3.3
3.3
3.3
3.5
3.5
1.4
0
3.3
0
3.3
0
0
1.5
1.8
1.1
-12.3/3.0
0
-12.3/3.0
0
0
1.4
0
0
3.3
3.3
3.3
3.3
3.3
3.3
0
0
3.3
0
3.3
E 8 A _ T X D
DC_PRT
HPRY
EEP_SCK
NCPU_N_INT
DIR_WCK
DIR_N_INT
N_FCT
S P R Y _ A
EEP_N_CS
DIR_N_INT
EEP_MISO
TUN_N_RST
KEY1
USB_BUSY
VOL_RA
H P R Y
C N V S S
DAC_N_RST
AMP_LMT
S P R Y _ B
E 8 A _ N _ C E
V O L _ M O S I
M T _ N _ S A
AMP_OLV
TUN_N_RST
REM_IN
L M T _ I
D C _ P R T
E 8 A _ S C L K
E 8 A _ N _ C E
K E Y 2
DIR_MOSI
DIR_SCK
D A C _ N _ C S
N C P U _ A D T _ M U T E
N C P U _ A D T _ M U T E
T U N _ S C L
E 8 A _ N _ E P M
T U N _ S D A
KEY2
DIR_SD0
I_PRT
E 8 A _ R X D
K E Y 1
L M T _ D C
N _ F C T
TUN_N_INT
M T _ S B
EEP_SCK
T R A N S _ R Y
DIR_MISO
V O L _ S C K
M T _ 5 C H
FLD_N_RST
FLD_N_CS
SPRY_A
TUN_SCL
TRANS_RY
E 8 A _ B U S Y
AMP_LMT
P R Y
C N V S S
E 8 A _ B U S Y
VOL_RB
HP_N_DET
EEP_MOSI
TUN_SDA
I _ P R T
VOL_RB
H P _ N _ D E T
REM_IN
EEP_N_CS
L M T _ P S 1
E 8 A _ S C L K
DAC_N_CS
M T _ N _ S W
PSW_N_DET
TUN_N_INT
M T _ S W
SPRY_B
VOL_RA
VOL_SCK
VOL_MOSI
FLD_SCK
FLD_MOSI
DIR_N_RST
DIR_N_CS
D C D C _ P O N
U S B _ V B U S _ P O N
STBY_LED
NCPU_PHOLD
DIR_PON
NCPU_SPI_SCK
N C P U _ S P I _ N _ C S
D I R _ S D 0
D I R _ W C K
L M T _ P S 2
THM1_PRT
PS2_PRT
PS1_PRT
DEST
ACPWR_DET
M T _ N _ S B
NCPU_N_INT
NCPU_SPI_MOSI
NCPU_SPI_MISO
NCPU_ADT_MUTE
NCPU_SPI_SCK
NCPU_SPI_N_CS
NCPU_N_RST
NCPU_PHOLD
DCDC_PON
USB_VBUS_PON
DIR_PON
I_PRT
USB_VBUS_PRT
L M T _ I
L M T _ P S 3
L M T _ 0 L V
DAC_N_RST
P S 2 _ P R T
P S 1 _ P R T
P S 1 _ P R T
P S 3 _ P R T
P S 3 _ P R T
EEP_MOSI
L M T _ P S 1
L M T _ P S 2
L M T _ P S 3
NCPU_RXD
EEP_MISO
MT_5CH
STBY_LED
FLD_N_RST
FLD_N_CS
+3.3S_PON
PRY
ACPWR_DET
D E S T
L M T _ D C
DRCT_LED
IN_RD
NET_RF
NET_RE
DRCT_LED
P D S W
F L _ P O N
REM_OUT
IN_RC
T U N I 2 C _ O N
NET_RF
NET_RE
IN_RC
MODE
E 8 A _ T X D
FLD_SCK
FLD_MOSI
IN_RD
E 8 A _ R X D
P S 2 _ P R T
P S 2 _ P R T
THM3_PRT
NCPU_PON
E 8 A _ N _ E P M
PCM/DSD_SEL
CPU_N_RST
NCPU_TXD
NCPU_MODE
NCPU_RXD
NCPU_TXD
PCM/DSD_SEL
NCPU_PON
DIR_N_RST
DIR_N_CS
DAC_ZERO_DET
NCPU_VBUSDRV
NCPU_MUTE0
DAC_ZERO_DET
NCPU_SPI_MISO
NCPU_SPI_MOSI
NCPU_N_INT
NCPU_VBUSDRV
NCPU_MUTE1
NCPU_MUTE0
NCPU_MUTE1
U S B _ V B U S _ P R T
T H M 3 _ P R T
A M P _ O L V
L M T _ 0 L V
T H M 1 _ P R T
PDSW
NCPU_N_RST
PSW_N_DET
MT_SB
MT_SW
CPU_N_RST
+3.3S_PON
DIR_MOSI
DIR_MISO
DIR_SCK
FL_PON
DIR_N_INT0
DIR_N_INT0
1 0 K
R 2 1 6
D G N D
D G N D
DGND
22
R243
22
R241
R 2 7 2
n o _ u s e
4 . 7 K
R 2 0 9
100K
R268
PL0.3
C 2 5 0
n o _ u s e
PL0.3
C B 2 7
5 2 0 4 5
1
2
3
4
5
6
7
8
9
R203
1
K
PL3.0
DAC_N_RST
D G N D
D G N D
1 0 0 P ( C H )
C 2 6 1
C 2 0 8
n o _ u s e
D G N D
4 7 0
R 2 7 6
5 6 K
R 2 5 3
C 2 0 5
n o _ u s e
22
R279
D G N D
D G N D
D G N D
1 / 1 0
C 2 4 5
C224
0.01/16(B)
D G N D
C 2 0 4
n o _ u s e
1 K
R 2 2 6
PL3.0
C 2 0 6
n o _ u s e
C 2 5 3
n o _ u s e
A 1 5 7 6 U B T L R
Q 2 0 8
C 2 5 2
n o _ u s e
C 2 5 1
n o _ u s e
D G N D
PL3.0
D G N D
R205
no_use
C 2 6 3
n o _ u s e
10K
R245
R202
9.1K
R 2 7 5
n o _ u s e
8 M H Z
X L 2 1
1
2
3
C220
0.01/16(B)
0.1/10(BJ)
C248
DIR_MISO
0
R239
10K
R248
D G N D
D G N D
100
R277
4 7 P ( C H )
C 2 1 1
C 2 3 8
n o _ u s e
1 K
R 2 5 1
T P 1 0 5 0
C 2 4 0
n o _ u s e
Q 2 0 3
H N 4 B 0 1 J E ( T E 8 5 L ,
B 1
E
B 2
C 2
C 1
1 0 0 P ( C H )
C 2 6 4
C217
0.1/10(BJ)
4 7 P ( C H )
C 2 1 0
4 7 P ( C H )
C 2 2 3
C 3 0 1
3 3 / 1 0
100
R280
C 2 6 2
n o _ u s e
C 2 0 7
n o _ u s e
D G N D
D G N D
10K
R214
C 2 5 4
n o _ u s e
C 2 3 9
n o _ u s e
D G N D
D G N D
C201
no_use
DGND
DGND
R 2 3 5
1 0 0 K
1 0 0
R 2 6 6
C 2 4 1
n o _ u s e
D G N D
NCPU_RXD
D G N D
R201
1K
C259
no_use
R246
100
10K
R204
C 2 2 2
n o _ u s e
DIR_WCK
D G N D
R 2 7 4
4 7 0
R 2 6 2
1 K
PL3.0
DGND
Q 2 0 5
A 1 5 7 6 U B T L R
C216
0.1/10(BJ)
100
R244
DGND
4 . 7 K
R 2 7 3
3 3 K
R 2 0 8
NCPU_N_INT
DIR_N_INT
R215
no_use
D G N D
DIR_SD0
D G N D
Q 2 0 9
n o _ u s e
100K
R270
T P 1 0 5 1
C 2 4 2
n o _ u s e
PL0.3
A 1 5 7 6 U B T L R
Q 2 1 0
D G N D
1 K
R 2 2 8
C 2 4 3
n o _ u s e
C260
1/25
C258
1/25
DIR_MOSI
D G N D
4 7 K
R 2 6 4
NCPU_TXD
10K
R212
C 2 3 7
n o _ u s e
4 7 K
R 2 6 5
R 2 2 2
4 7
DAC_N_CS
R269
no_use
10K
R237
0.1/10(BJ)
C247
0 . 1 / 1 0 ( B J )
C 2 4 6
D G N D
Q 2 0 1
H N 4 B 0 1 J E ( T E 8 5 L ,
B 1
E
B 2
C 2
C 1
C 2 3 5
n o _ u s e
DIR_SCK
C 2 4 4
n o _ u s e
4 . 7 K
R 2 7 1
D G N D
22
R278
NCPU_N_INT
D G N D
C 2 0 3
n o _ u s e
C 2 0 2
n o _ u s e
T P 1 1 0 0
D G N D
T P 1 0 8 8
C269
4.7/6.3
+ 3 . 3 M
C267
4.7/6.3
R P 1 3 0 Q 3 3 1 D - T R - F
Y C 2 8 8 A 0
VDD
GND
VOUT
CE/CE
+ 5 . 5 V
R P 1 3 0 Q 3 3 1 D - T R - F
Y C 2 8 8 A 0
VDD
GND
VOUT
CE/CE
+ 3 . 3 S
C268
1/25
C266
1/25
D G N D
C 2 4 9
n o _ u s e
1 K
R 2 2 9
1 K
R 2 2 3
PL0.3
DGND
Q 2 0 2
H N 4 B 0 1 J E ( T E 8 5 L ,
B 1
E
B 2
C 2
C 1
PL3.0
NCPU_ADT_MUTE
+ 3 . 3 M
+ 3 . 3 M
+ 3 . 3 S
+3.3S
+ 3 . 3 S
+3.3S
+3.3S
+3.3S
+ 3 . 3 M
+ 3 . 3 M
+ 3 . 3 M
+ 3 . 3 M
+ 3 . 3 M
+ 3 . 3 M
+ 3 . 3 D I R
+ 3 . 3 M
+ 3 . 3 S
+ 3 . 3 S
+ 3 . 3 M
+ 3 . 3 M
+ 3 . 3 M
+ 3 . 3 S
+3.3M
+3.3DIR
DGND
+3.3M
DGND
+3.3S
NCPU_SPI_MOSI
NCPU_SPI_MISO
NCPU_SPI_SCK
NCPU_SPI_N_CS
NCPU_N_RST
NCPU_PHOLD
DIR_N_CS
DIR_N_RST
DCDC_PON
USB_VBUS_PON
DIR_PON
+3.3S
A1576UBTLR
Q207
330
R267
USB_VBUS_PRT
Q 2 0 6
A 1 5 7 6 U B T L R
DGND
PL3.0
Q 2 0 4
C 4 0 8 1 U B T L R
PL0.3
+3.3S
10K
R282
DGND
10K
R240
+ 5 A
15K
R210
D G N D
+ 5 . 5 V
18K
R206
D G N D
10K
R207
C 2 1 3
n o _ u s e
C 2 1 2
n o _ u s e
22
R260
CB24
52151
P N 2 1
n o _ u s e
R351
100X4
R352
100X4
R353
100X4
1
2
4
5
7
8
3
6
R354
100X4
R355
100X4
R219
100
+ 3 . 3 M
C B 2 8
n o _ u s e
+ 3 . 3 M
R234
470K
C B 2 9
P H I
D205
1SS355VM
+ 5 . 5 V
DGND
CB21
5 2 0 4 4
R356
100X4
1
2
4
5
7
8
3
6
1 0 0 0 P ( B )
C 2 3 4
1 0 0 0 P ( B )
C 2 2 1
R 3 5 9
1 0 K X 4
R 3 6 2
4 7 X 4
R 3 6 3
4 7 X 4
PCM/DSD_SEL
NCPU_PON
CB25
52151
0
J205
+ 3 . 3 S
R225
no_use
D G N D
R227
no_use
R 3 6 1
1 0 0 K X 4
R 3 6 0
1 0 0 K X 4
CB23
52044
R230
no_use
+ 3 . 3 M
D G N D
+ 3 . 3 S
R 2 8 3
1 0 K
C B 3 0
I M S A - 9 6 0 4 S - 0 5 C
V U 2 7 0 5 0
1
2
3
4
5
R365
10K
D G N D
0
J207
R 3 6 6
1 0 K
+ 3 . 3 S
D G N D
J368 no_use
DAC_ZERO_DET
R368
10K
DGND
NCPU_VBUSDRV
22
R236
R371
22
R370
no_use
R369
22
R372
no_use
NCPU_MUTE0
NCPU_MUTE1
R 3 5 7
1 0 0
R 3 7 3 1 0 0
R 3 7 4 1 0 0
R 3 5 8
1 0 0
0
J208
A
0
J209
A
0
J210
A
I C 2 2
R 1 E X 2 5 0 3 2 A T A 0 0 I
S
Q
W
V S S
5 D
6 C
7 H O L D
8 V C C
2 2
R 2 1 7
R247
47
R364
100
R375
100
1 0 K
R 2 1 8
R367
10K
R919
10K
C 2 1 4
0 . 1 / 1 6
C218
0.01(B)
C226
0.01(B)
C227
0.01(B)
C228
0.01(B)
C229
0.01(B)
C230
0.01(B)
C232
0.01(B)
C233
0.01(B)
C 2 5 5
0 . 0 1 ( B )
C 2 7 5
n o _ u s e
R213
no_use
C 2 3 6
n o _ u s e
R211
no_use
C 2 7 4
n o _ u s e
22
R238
+3.3M
DIR_N_INT0
+ 3 . 3 D I R
1000P(B)
C256
P14_0
T X D
D G N D
BYTE
C N V s s
A N 0 _ 2
C L K 1
N_INT0
N_INT1
P3_2
A N 0 _ 0
S C L 0
N_INT2
P 1 1 _ 3
E E P R O M
SDA2
P 6 _ 0
P12_2
S C L K
TXD7
P 1 3 _ 7
/ R E S
P 1 _ 0
P4_4
to 003.sht
(NCPU)
P 5 _ 4
P 1 2 _ 7
CLK4
SIN4
D I G I T A L 1 : C P U
P 1 3 - 6
V S S
P2_0
P4_2
N_INT7
P1_1
SCL2
P3_7
RXD1
TA2IN
VSS
P 6 _ 4
P12_4
A N 0 _ 4
P1_4
P4_1
RXD7
VCC1
CEC
S D A 0
SOUT3
P 1 3 _ 2
VCC1
P4_0
A N 0
SIN3
TXD1
VREF
A N 5
C L K 0
TA4IN
P8_6
A V S S
P 5 _ 5
TXD6
( 1 6 0 8
0 . 5 % )
P 1 3 _ 1
P 1 3 _ 4
P 1 1 _ 5
P2_3
P 1 3 _ 3
P7_2
P 1 1 _ 2
SCL5
CLK7
P 0 _ 7
B U S Y
VCC2
A N 0 _ 5
t o O P E ( 1 )
P2_1
P4_3
P 5 _ 7
Destination
P 1 1 _ 7
P 5 _ 6
A N 1
P 1 3 - 5
TA1IN
A N 2
P 5 _ 0
P 1 1 _ 6
A N 7
P 1 2 _ 6
P14_1
SD5
P 1 1 _ 1
P7_4
AVCC
P1_7
P3_0
P 5 _ 1
P 1 1 _ 0
P 1 3 _ 0
B
A N 0 _ 1
N_INT4
A N 4
N_INT6
P3_3
( 3 2 k b i t s )
A N 3
RXD6
P8_0
P2_7
P3_1
A N 6
P2_6
P2_2
P 1 2 _ 5
M U T E
L / R
VSS
SOUT4
CLK3
A
XIN
P 5 _ 2
XOUT
P9_4
A N 0 _ 3
/ E P M
P12_1
to 002.sht
(DIR)
P3_5
/ C E
P 1 1 _ 4
CNVSS
/RESET
FCT
P12_3
N C
DA0
P 0 _ 6
P3_4
+ 5 D
M U T E
S u b W o o f e r
P12_0
P8_7
P 5 _ 3
P3_6
R X D
DGND
FLD_MOSI
FLD_SCK
STBY_LED
KEY1
REM_IN
FLD_N_RST
+3.3M
PSW_N_DET
KEY2
VOL_RB
+3.3DSP
VOL_RA
FLD_N_CS
PS1_PRT
PS2_PRT
VID_PON
R_200_DET
to MAIN(2)
CPU_N_RST
+3.3M
PRY
ACPWR_DET
DGND
DEST
to MAIN(3)
SCL
SDA
RST
GPIO2
+3.3S
THM2_PRT
DGND
THM1_PRT
M
3
.
3
+
S
3
.
3
+
THM3_PRT
SPRY_5CH
HPRY
MUTE_SW
PS1_PRT/PDSW
DC_PRT
I_PRT
VOL_MOSI
AMP_OLV
MUTE_5ch
SPRY_SB/SPRY_B
MUTE_SB/MUTE_Z2
VOL_SCK
HP_N_DET
TRANS_RY
AMP_LMT
DG
D I A G _ F C T
to 003.sht
(NCPU)
PS Protection
to 002.sht
to 003.sht
(DIR&NCPU)
t o M A I N ( 2 )
I C / C B / X L : 9 1 - 9 9
A r r a y R : 9 4 1 - 9 9 9
O H T E R : 9 0 1 - 9 9 9
IN_RD
DGND
PRY
+5.5V
f o r
F A T E S T
IN_RC
DRCT_LED
FL_PON
(2125) A-side
NET_RF
NET_RE
to OPE(4)
A-side
N_INT3
M 9 5 3 2 0 - R D W 6 T P
B R 2 5 S 3 2 0 F V T - W E 2
R e n e s a s
m
h
o
R
0
A
4
1
9
D
Y
Y E 1 8 2 B 0
S T m i c r o
Y G 2 6 8 A 0
R 1 E X 2 5 0 3 2 A T A 0 0 I
N O T I C E
U.S.A
G
CANADA
EUROPE
L
CHINA
AUSTRALIA
SINGAPORE
KOREA
GENERAL
U
C
T
A
K
R
JAPAN
(model)
B
BRITISH
J
SOUTH EUROPE
E
V
TAIWAN
F
RUSSIAN
P
LATIN AMERICA
S
BRAZIL
H
THAI
RESISTOR
REMARKS
NO MARK
PARTS
NAME
CARBON
CARBON
METAL
METAL
METAL
FIRE
CEMENT
SEMI
FILM RESISTOR
FILM RESISTOR
OXIDE FILM RESISTOR
FILM RESISTOR
PLATE RESISTOR
PROOF CARBON FILM RESISTOR
MOLDED RESISTOR
VARIABLE
RESISTOR
(P=5)
(P=10)
CHIP RESISTOR
REMARKS
CAPACITOR
PARTS NAME
NO
NO
MARK
MARK
ELECTROLYTIC
CAPACITOR
CERAMIC CAPACITOR
POLYESTER FILM CAPACITOR
POLYSTYRENE FILM CAPACITOR
MICA CAPACITOR
POLYPROPYLENE
FILM CAPACITOR
SEMICONDUCTIVE CERAMIC CAPACITOR
P
TANTALUM
CAPACITOR
TUBULAR
S
CAPACITOR
CERAMIC
FILM
SULFIDE
POLYPHENYLENE
CAPACITOR
Timer (16-bit)
Internal peripheral functions
Inputs (timer B): 6
Three-phase motor control circuit
Outputs (timer A): 5
Watchdog timer
(15-bit)
Remote control signal
receiver
(2 circuits)
PWM function (8-bit x 2)
CEC function
Real-time clock
VCC1 ports
VCC2 ports
A/D converter
(10-bit resolution X 26 channels)
System clock generator
PLL frequency synthesizer
On-chip oscillator (125 kHz)
High-speewd on-chip oscillator
X
IN
-X
OUT
X
CIN
-X
COUT
Port P0
8
Port P1
8
Port P2
8
Port P3
8
Port P4
8
Port P5
8
Port P12
8
Port P13
8
Port P14
2
Port P11
8
Port P10
8
Port P9
8
Port P8
8
Port P7
8
Port P6
8
ISP
USP
INTB
SB
CRC arithmetic circuit
(CRC-CCITT or CRC-16)
DMAC (4 channels)
Voltage detecter
On-chip debugger
Power-on reset
Multiplier
Memory
ROM
RAM
FB
A1
FLG
PC
UART or
clock synchronous serial I/O
Clock synchronous serial I/O
Multi-master I
2
C-bus interface
(6 channels)
(8 bit x 2 channels)
(1 channel)
D/A converter
(8-bit resolution X 2 circuits)
M16C/60 series
Microprocessor core
R0L
R0H
R1H
R1L
R2
R3
FB
A1
A0
IC22
: R1EX25032ATA00A
Serial peripheral interface 32 k EEPROM (4-kword × 8-bit)
Vcc
8
Vss
4
S
1
W
3
C
6
Serial-parallel converter
Y-select and Sense amp.
Memory array
High voltage generator
HOLD
7
D
5
Q
2
Control logic
Address generator
Y
decoder
X
decoder
IC21
: R5F3651TNFC
Single chip 16-bit microprocessor
V
DD
CE
Vref
4
3
1
2
Current Limit
V
OUT
GND
Pin No.
1
2
3
4
Symbol
V
OUT
GND
CE
V
DD
Description
Output Pin
Ground Pin
Chip Enable ("H" Active)
Input Pin
IC25, 28
: RP130Q331D-TR-F
Voltage regulator
EEPROM
to DIGITAL 2/3, 3/3
to DIGITAL 2/3
to DIGITAL 3/3
to DIGITAL 2/3
Details of colored lines
Red / full line:
Power supply (+)
Red /dashed line: Power supply (-)
Orange: Signal
detect
Yellow: Clock
Green: Protection
detect
Brown: Reset
signal
Blue:
Panel key input
No replacement part available.
(for factory)
Writing port
Содержание R-N602
Страница 3: ... FRONT PANEL U model R model REAR PANELS 3 R N602 R N602 ...
Страница 4: ...K model A model B model 4 R N602 R N602 ...
Страница 5: ...G model L model J model 5 R N602 R N602 ...
Страница 108: ...MEMO 109 R N602 R N602 ...
Страница 109: ...R N602 ...