A
1
2
3
4
5
6
7
8
9
10
K
J
I
H
G
F
E
D
C
B
L
N
M
61
R-N402/R-N402D
DIGITAL IN
E8A_TXD
EEP_SCK
D I R _ N _ I N T 0
S P R Y _ A
EEP_N_C
S
EEP_MIS
O
TUN_N_RST
VOL_R
A
H P R Y
D A C _ N _ R S T
S P R Y _ B
E 8 A _ N _ C E
V O L _ M O S I
L M T _ I
E 8 A _ S C L K
E 8 A _ N _ C E
D I R _ M O S I
D A C _ N _ C S
N C P U _ A D T _ M U T E
T U N _ S C L
T U N _ S D A
E8A_RXD
N _ F C T
TUN_TUNED
EEP_SCK
V O L _ S C K
FLD_N_RST
FLD_N_C
S
P R Y
E 8 A _ B U S Y
EEP_MOS
I
VOL_R
B
REM_I
N
EEP_N_C
S
D A C _ N _ C S
FLD_SCK
FLD_MOS
I
DIR_N_RST
DIR_N_C
S
STNBY_LED
N C P U _ S P I _ N _ C S
N C P U _ N _ I N T
N C P U _ S P I _ M O S I
N C P U _ S P I _ M I S O
N C P U _ S P I _ S C K
N C P U _ S P I _ N _ C S
N C P U _ N _ R S T
U S B _ V B U S _ P R T
DAC_N_RST
P S 2 _ P R T
EEP_MOS
I
NCPU_RX
D
EEP_MIS
O
NET_R
F
MOD
E
PCM/DSD_SEL
NCPU_TX
D
N C P U _ R X D
N C P U _ T X D
P C M / D S D _ S E L
N C P U _ P O N
D I R _ N _ R S T
D I R _ N _ C S
DAC_ZERO_DET
NCPU_SPI_MISO
NCPU_SPI_MOSI
NCPU_N_IN
T
USB_VBUSDR
V
N C P U _ M U T E 0
N C P U _ M U T E 1
U S B _ V B U S _ P R T
+3.3S_PON
DIR_MOS
I
DIR_MIS
O
DIR_SC
K
DIR_N_INT
0
M A I N _ N _ M U T E
R E C _ N _ M U T E
I _ P R T
THM
1
N C P U _ M U T E 1
NCPU_SPI_SCK
NCPU_MUTE
0
BT_LE
D
WIFI_LE
D
NET_R
E
LED_OF
F
FLD_N_RST
FLD_N_C
S
FLD_MOS
I
FLD_SC
K
REM_I
N
STNBY_LED
LED_OF
F
PWR_N_DET
WIFI_LE
D
BT_LE
D
REC_N_MUT
E
DC_PR
T
I_PRT
HPR
Y
SPRY_
B
SPRY_
A
TUN_SD
A
TUN_SC
L
MAIN_N_MUT
E
DAC_R
DAC_L
DES
T
PR
Y
ACPWR_DET
CPU_N_RST
N_FCT
L M T _ P S 3
L M T _ I
L M T _ P S 2
L M T _ P S 1
L M T _ D C
L M T _ D C
L M T _ P S 1
L M T _ P S 3
L M T _ P S 2
NCPU_PHOL
D
D I R _ M I S O
N C P U _ P H O L D
N C P U _ A D T _ M U T E
U S B _ V B U S D R V
D A C _ Z E R O _ D E T
CNVS
S
D I R _ S C K
+ 3 . 3 S _ P O N
NCPU_PO
N
ADR
ADL
P S 3 _ P R T
D C _ P R T
K E Y 1
PWR_N_DET
+3.3D_PON
C P U _ N _ R S T
E 8 A _ S C L K
E 8 A _ T X D
E 8 A _ R X D
C N V S S
E 8 A _ B U S Y
E 8 A _ N _ E P M
ACPWR_DET
VBUS_PO
N
V B U S _ P O N
P S 3 _ P R T
KEY
0
KEY
1
TUN_TUNED
TUN_N_RST
D I R _ W C K 1
D I R _ S D O 1
D I R _ S D O 1
D I R _ W C K 1
PS1_PR
T
PWR_N_DET
P W R _ N _ D E T
THM
3
HP_N_DE
T
E 8 A _ N _ E P M
NCPU_N_RS
T
T H M 1
K E Y 0
P S 1 _ P R T
+ 3 . 3 D _ P O N
VOL_SC
K
VOL_MOS
I
N C P U _ M O D E
H P _ N _ D E T
NET_R
F
VOL_R
B
VOL_R
A
T H M 3
DIR_N_INT
D I R _ N _ I N T
NET_R
E
D E S T
D G N D
22
R334
22
R331
R 3 1 2
n o _ u s e
C B 3 0 5
5 2 0 4 5
n o _ u s e
1
2
3
4
5
6
7
8
9
R
3
0
3
1
K
D A C _ N _ R S T
D G N D
D G N D
1 / 1 0
C 3 0 3
1 K
R 3 1 7
R
3
0
2
9
.
1
K
8 M H Z
X L 3 0 1
1
2
3
0 . 1 / 1 0 ( B J )
C 3 0 8
10
K
R342
D G N D
T P 3 3 3
10
K
R310
D G N D
D G N D
1 0 0
R 3 5 0
N C P U _ R X D
R
3
0
1
1
K
R 3 4 7
1 K
PL3.
0
3 3 K
R 3 1 3
N C P U _ N _ I N T
D I R _ N _ I N T 0
R311
no_use
T P 3 3 4
PL0.
3
1 K
R 3 1 9
D I R _ M O S I
D G N D
N C P U _ T X D
10
K
R30
4
47
K
R34
9
R 3 2 1
4 7
D A C _ N _ C S
0.1/10(BJ
)
C30
6
0 . 1 / 1 0 ( B J )
C 3 0 2
1 K
R 3 2 0
1 K
R 3 1 6
N C P U _ A D T _ M U T E
+ 3 . 3 M
+ 3 . 3 M
+ 3 . 3 S
+ 3 . 3 S
+ 3 . 3 M
+ 3 . 3 M
+ 3 . 3 M
N C P U _ S P I _ M O S I
N C P U _ S P I _ M I S O
N C P U _ S P I _ S C K
N C P U _ S P I _ N _ C S
N C P U _ N _ R S T
D I R _ N _ C S
D I R _ N _ R S T
V B U S _ P O N
+ 3 . 3 D _ P O N
U S B _ V B U S _ P R T
+ 5 N E T
D G N D
+ 3 . 3 D
18
K
R30
8
D G N D
10
K
R30
9
22
R34
5
C B 3 0 6
n o _ u s e
R 3 5 7
4 7 X 4
R 3 5 8
4 7 X 4
P C M / D S D _ S E L
N C P U _ P O N
+ 3 . 3 S
R33
8
no_us
e
D G N D
R 3 5 3
1 0 0 K X 4
R 3 5 2
1 0 0 K X 4
R 3 4 6
1 0 K
D A C _ Z E R O _ D E T
22
R32
4
R33
0
22
R32
8
22
R32
6
22
N C P U _ M U T E 0
N C P U _ M U T E 1
R 3 2 2
1 0 0
R 3 1 8 1 0 0
I C 3 0 1
R 1 E X 2 5 0 3 2 A T A 0 0 I
S
Q
W
V S S
D
C
H O L D
V C C
+ 3 . 3 M
0 . 1 / 1 0 ( B J )
C 3 1 0
C B 3 0 1
2 5 F M N - B T K
+3.3S
DGN
D
22
R32
3
DGN
D
DGN
D
+3.3M
VP
VP
E
VP
VP
E
AGN
D
DAC_R
DAC_L
+3.3M
C 3 1 5
0 . 1 / 1 0 ( B J )
AC_PW
R
+ 5 . 5 V
DGN
D
PRY_I
N
C 3 1 3
n o _ u s e
W 3 0 1
C 3 1 4
1 / 2 5
D 3 0 6
1 S S 3 5 5 V M
+ 3 . 3 M
Q 3 0 6
C 4 0 8 1 U B T L R
P R Y _ O N
D305
1SS355V
M
D302
1SS355V
M
Q 3 0 8
D T C 0 4 4 E U B T L
C 3 0 9
0 . 0 1 ( B )
A C _ P W R
C304
0.01(B)
D G N D
C 3 0 7
2 . 2 / 5 0
Q 3 0 7
C 4 0 8 1 U B T L R
D 3 0 4
1 S S 3 5 5 V M
D301
1SS355V
M
P R Y _ I N
D303
1SS355V
M
PL0.3
D G N D
Q 3 0 2
H N 4 B 0 1 J E ( T E 8 5 L ,
B 1
E
B 2
C 2
C 1
PL3.
0
D G N D
Q 3 0 5
A 1 5 7 6 U B T L R
D G N D
Q 3 0 1
H N 4 B 0 1 J E ( T E 8 5 L ,
B 1
E
B 2
C 2
C 1
PL3.0
+3.3S
D G N D
PL3.
0
PL3.
0
+3.3
S
PL3.
0
D G N D
PL0.
3
Q 3 0 3
A 1 5 7 6 U B T L R
Q 3 0 4
A 1 5 7 6 U B T L R
D I R _ M I S O
N C P U _ P H O L D
U S B _ V B U S D R V
D G N D
R
3
5
6
1
K
R
3
5
5
9
.
1
K
DGND
C 3 1 2
1 0 / 6 . 3
D 3 0 7
1 S S 3 5 5 V M
R 3 5 1
1 M
R
3
5
4
1
K
C316
0.1/10(BJ
)
Q 3 0 9
H N 4 B 0 1 J E ( T E 8 5 L ,
B 1
E
B 2
C 2
C 1
+3.3
M
I C 3 0 3
V -
+ 3 . 3 M
D 3 0 8
R B 5 2 1 S - 3 0 T E 6 1
I C 3 0 3
S N 7 4 L V C 1 G 1 7 D C K R
D G N D
+ 3 . 3 M
D I R _ S C K
+ 3 . 3 S _ P O N
AD
R
AD
L
+3.3S
PRY_O
N
CB307
PHI
1
2
3
DGND
+ 5 . 5 V
D G N D
D G N D
1 0 K
R 3 1 5
2 2
R 3 1 4
22
R325
C32
2
0.1/10(BJ
)
C32
3
0.1/10(BJ
)
C
325
0.1/10(BJ)
C319
0.1/10(BJ)
C 3 0 1
0 . 1 / 1 0 ( B J )
R343
100K
R329
100K
R 3 4 0
1 0 0
R332
10
0
R335
10
0
R344
47
K
R333
1M
C3
0
5
1/10
R34
8
10
K
10
K
R30
7
R336
10
K
R 3 2 7
1 0
R 3 3 7
2 . 2 K
R33
9
no_us
e
R34
1
47
C B 3 0 2
5 2 4 1 8
C B 3 0 3
5 2 4 1 8
0.1/10(BJ)
C31
8
27
K
R30
6
+ 5 A
+8.5V
R 3 6 0
1 0 K
R 3 6 1
1 0 K
+ 3 . 3 M
+ 3 . 3 M
R 3 6 2
1 0 K
R 3 6 3
1 0 K
DGN
D
D I R _ S D O 1
D I R _ W C K 1
+ 3 . 3 M
R 3 6 8
1 0 0
R36
7
no_us
e
C326
0.1/10(BJ)
C320
0.1/10(BJ)
C321
0.1/10(BJ)
R 3 7 0
2 2
+ 3 . 3 D _ P O N _ 1
W 3 5 1
S A N - P H
+ 3 . 3 S
R36
6
10K
R 3 6 5
n o _ u s e
R37
3
10
K
R369
2.2K
+ 3 . 3 S
C 3 3 0
1 0 0 0 P ( B )
C 3 3 1
1 0 0 0 P ( B )
C 3 3 2
1 0 0 0 P ( B )
C 3 3 3
1 0 0 0 P ( B )
D G N D
R37
4
1K
+ 3 . 3 S
D I R _ N _ I N T
R 3 7 2
2 . 2 K
R 3 7 1
2 . 2 K
R652
47
K
0.01(B)
C311
P N 3 0 1
C32
4
0.1/10(BJ
)
33
K
R35
9
P14_
0
T X D
T C K
D G N D
BYTE
G N D
C N V s s
A N 0 _ 2
C L K 1
N_INT0
N_INT1
P3_
2
A N 0 _ 0
S C L 0
N_INT2
P 1 1 _ 3
E E P R O M
E8
a
SDA2
P 6 _ 0
P12_2
S C L K
/ E P M
TXD
7
P 1 3 _ 7
/ R E S
/ C E
P 1 _ 0
P4_
4
P 5 _ 4
P 1 2 _ 7
CLK4
SIN4
D I G I T A L 1 : C P U
P 1 3 - 6
V S S
P2_
0
P4_
2
N_INT
7
P1_
1
SCL2
P3_
7
RXD1
TA2I
N
VS
S
P 6 _ 4
P12_4
A N 0 _ 4
P1_
4
P4_
1
RXD
7
VCC1
CE
C
S D A 0
SOUT
3
P 1 3 _ 2
VCC1
P4_
0
A N 0
SIN3
TXD1
VREF
A N 5
C L K 0
TA4I
N
P8_6
A V S S
P 5 _ 5
TXD
6
P 1 3 _ 1
P 1 3 _ 4
P 1 1 _ 5
P2_
3
P 1 3 _ 3
P7_2
P 1 1 _ 2
SCL5
CLK
7
P 0 _ 7
B U S Y
VCC
2
A N 0 _ 5
to In-circuit
Programme
r
P2_
1
P4_
3
P 5 _ 7
T T X D
Destinatio
n
P 1 1 _ 7
P 5 _ 6
A N 1
P 1 3 - 5
TA1I
N
A N 2
P 5 _ 0
P 1 1 _ 6
A N 7
P 1 2 _ 6
P14_
1
SD
5
P 1 1 _ 1
P7_4
AVCC
P1_
7
P3_
0
P 5 _ 1
P 1 1 _ 0
P 1 3 _ 0
B
A N 0 _ 1
N_INT
4
A N 4
N_INT
6
P3_
3
( 3 2 k b i t s )
A N 3
RXD
6
P8_0
P2_
7
P3_
1
A N 6
P2_
6
P2_
2
P 1 2 _ 5
VS
S
SOUT
4
CLK3
A
XI
N
P 5 _ 2
XOUT
P9_4
A N 0 _ 3
/ E P M
P12_1
P3_
5
/ C E
P 1 1 _ 4
CNVS
S
/RESET
/ T R E S
FC
T
P12_3
N C
DA
0
P 0 _ 6
P3_
4
+ 5 D
T R X D
P12_0
T M O D E
N C
P8_7
P 5 _ 3
T B U S Y
T V c c d
P3_
6
R X D
D I A G _ F C T
To Network Modul
e
PS Protectio
n
(2125
)
A-sid
e
N_INT
3
M 9 5 3 2 0 - R D W 6 T P
B R 2 5 S 3 2 0 F V T - W E 2
R e n e s a s
m
h
o
R
0
A
4
1
9
D
Y
Y E 1 8 2 B 0
S T m i c r o
Y G 2 6 8 A 0
R 1 E X 2 5 0 3 2 A T A 0 0 I
t o P C B T H M
+3.3S
DGN
D
THM
1
t o F L
t o P C B M A I N
t o P C B M A I N
DGN
D
t o P C B A C D C
DGN
D
DGN
D
DGN
D
PRY_IN
DGN
D
+5.5V
+5.5V
DES
T
+5.5V
+5.5V
AC_PWR
002.sht
To DI
R
002.sht
To DA
C
002.sh
t
F o r c e R E S E T
O U T P U T C H E C K I N F C T
R e f e r e n c e N o 3 0 1 ~
D A C O u t p u t i s r e v e r s e d
D A C _ L - > R c h a n n e l
D A C _ R - > L c h a n n e l
IC301
: R1EX25032ASA00I
4096 x 8-bit SPI serial interface EEPROM
Vcc
8
Vss
4
S
1
W
3
C
6
Serial-parallel converter
Y-select and Sense amp.
Memory array
High voltage generator
HOLD
7
D
5
Q
2
Control logic
Address generator
Y
decoder
X
decoder
DMAC
(4 channels)
Internal peripheral functions
UART or
clock synchronous serial I/O
(6 channels)
System clock generator
XIN-XOUT
XCIN-XCOUT
PLL frequency synthesizer
On-chip oscillator (125 kHz)
High-speed on-chip oscillator
Clock synchronous serial I/O
(8 bit x 2 channels)
Notes:
1. ROM size depends on MCU type.
2. RAM size depends on MCU type.
8
8
8
8
8
8
Port P5
Port P4
Port P3
Port P2
Port P1
Port P0
VCC2 ports
M16C/60 Series CPU core
R1H
R1L
R0H
R0L
R3
R2
A0
A1
FB
Multiplier
ROM
(1)
Memory
RAM
(2)
SB
ISP
USP
INTB
PC
FLG
CRC arithmetic circuit
(CRC-CCITT or CRC-16)
Three-phase
motor control circuit
Timer (16 bit)
Outputs (timer A): 5
Inputs (timer B): 6
VCC1 ports
Real-time clock
PWM function (8 bit x 2)
Remote control signal
receiver (2 circuits)
Watchdog timer
(15 bit)
A/D converter
(10-bit resolution x 26
channels)
D/A converter
(8-bit resolution x 2
circuits)
Multi-master I
2
C-bus interface
(1 channel)
CEC function
8
8
Port P13
Port P12
Port P7
Port P8
Port P9
Port P6
2
Port P14
Port P11
Port P10
8
8
8
8
8
8
On-chip debugger
Voltage detector
Power-on reset
IC302
: R5F3651TNFC
CPU core and flash memory
IC103
: SN74LVC1G17DCKR
Single schmitt-trigger buffer
1
2
3
5
4
NC
A
GND
VCC
Y
INPUT
A
OUTPUT
Y
L
H
L
H
DIGITAL (1)
EEPROM
N O T I C E
U . S . A
G
C A N A D A
E U R O P E A N S T A N D A R D
L
C H I N A
A U S T R A L I A
S I N G A P O R E
K O R E A
G E N E R A L
U
C
T
A
K
R
J A P A N
( m o d e l )
B
B R I T I S H
J
S O U T H E U R O P E
E
V
T A I W A N
F
R U S S I A N
P
L A T I N A M E R I C A
S
B R A Z I L
H
T H A I
R E M A R K S
C A P A C I T O R
P A R T S
N A M E
N O
N O
M A R K
M A R K
E L E C T R O L Y T I C
C A P A C I T O R
C E R A M I C
C A P A C I T O R
P O L Y E S T E R F I L M
C A P A C I T O R
P O L Y S T Y R E N E
F I L M
C A P A C I T O R
M I C A
C A P A C I T O R
P O L Y P R O P Y L E N E
F I L M
C A P A C I T O R
S E M I C O N D U C T I V E C E R A M I C C A P A C I T O R
P
S O L I D E L E C T R O L Y T I C
C A P A C I T O R
T U B U L A R
C A P A C I T O R
C E R A M I C
R E S I S T O R
R E M A R K S
N O M A R K
P A R T S
N A M E
C A R B O N
C A R B O N
M E T A L
M E T A L
M E T A L
F I R E
C E M E N T
S E M I
F I L M R E S I S T O R
F I L M R E S I S T O R
O X I D E F I L M R E S I S T O R
F I L M
R E S I S T O R
P L A T E R E S I S T O R
P R O O F C A R B O N
F I L M R E S I S T O R
M O L D E D R E S I S T O R
V A R I A B L E
R E S I S T O R
( P = 5 )
( P = 1 0 )
C H I P R E S I S T O R
No replacement part available.
(for factory)
to DIGITAL 2/3
to DIGITAL 2/3
to DIGITAL 2/3
28.7V
3.30V
3.30V
3.30V
28.8V
3.30V
3.30V
3.30V
4.99V
4.98V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
5.51V
5.51V
8.03V
■
SCHEMATIC DIAGRAMS
DIGITAL 1/3
★
All voltages are measured with a 10M
Ω
/V DC electronic voltmeter.
★
Components having special characteristics are marked
⚠
and must be replaced
with parts having specifications equal to those originally installed.
★
Schematic diagram is subject to change without notice.
Details of colored lines
R
ed / full line
:
P
ower supply (+)
R
ed /dashed line
:
P
ower supply (-)
Orange
:
S
ignal detect
Y
ellow
:
Clock
G
reen
:
P
rotection detect
B
rown
:
R
eset signal
B
lue
:
P
anel key input
Содержание R-N402
Страница 3: ...3 R N402 R N402D R N402 R N402D FRONT PANELS R N402 R N402D ...
Страница 4: ...4 R N402 R N402D R N402 R N402D REAR PANELS R N402 U model R N402 R model R N402 T model ...
Страница 5: ...5 R N402 R N402D R N402 R N402D R N402 K model R N402 A model R N402 B G models ...
Страница 6: ...6 R N402 R N402D R N402 R N402D R N402 L model R N402 S model R N402D B G models ...
Страница 51: ...51 R N402 R N402D J I H G F E D C B A 1 2 3 4 5 6 7 Side B DIGITAL 1 Side B DIGITAL 2 ...
Страница 60: ...60 R N402 R N402D MEMO MEMO ...
Страница 82: ...83 R N402 R N402D R N402 R N402D MEMO ...
Страница 83: ...R N402 R N402D ...