Yamaha EMX 5000-12, Руководство по обслуживанию

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EMX5000-12/20
21
PIN
NO.
I/O FUNCTION NAME
PIN
NO.
I/O FUNCTION NAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
DAUX
HDLT
DOUT
VFL
OPT
SYNC
MCC
WC
MCB
MCA
SKSY
XI
XO
P256
LOCK
Vss
TC
DIM1
DIM0
DOM1
DOM0
KM1
I
O
O
O
O
O
O
O
O
O
I
I
O
O
O
O
I
I
I
I
I
Auxiliary input for audio data
Asynchronous buffer operation flag
Audio data output
Parity flag output
Fs x 1 Synchronous output signal for DAC
Fs x 1 Synchronous output signal for DSP
Fs x 64 Bit clock output
Fs x 1 Word clock output
Fs x 128 Bit clock output
Fs x 256 Bit clock output
Clock synchronization control input
Crystal oscillator connection or external
clock input
Crystal oscillator connection
VCO oscillating clock connection
PLL lock flag
Logic section power (GND)
PLL time constant switching output
Data input mode selection
Data input mode selection
Data output mode selection
Data output mode selection
Clock mode switching input 1
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
RSTN
Vdda
CTLN
PCO
(NC)
CTLP
Vssa
TSTN
KM2
KM0
FS1
FS0
CSM
EXTW
DDIN
LR
Vdd
ERR
EMP
CD0
CCK
CLD
I
I
O
I
I
I
I
O
O
I
I
I
O
O
O
O
I
I
System reset input
VCO section power (+5V)
VCO control input N
PLL phase comparison output
VCO control input P
VCO section power (GND)
Test terminal. Open for normal use
Clock mode switching input 2
Clock mode switching input 0
Channel status sampling frequency
display output 1
Channel status sampling frequency
display output 0
Channel status output method selection
External synchronous auxiliary input
word clock
EIAJ (AES/EBU) data input
PLL word clock output
Logic section power (+5 V)
Data error flag output
Channel status emphasis control code
output
3-wire type microcomputer interface data
output
3-wire type microcomputer interface clock
input
3-wire type microcomputer interface load
input
YM3436DK (XG948E0) DIR2 (Digital Format Interface Receiver)
DSP-SPX: IC103
PIN
NO.
I/O FUNCTION NAME
PIN
NO.
I/O FUNCTION NAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VREFH
AINR+
AINR-
AINL+
AINL-
VA
AGND
DIF0
DIF1
LRCK
SCLK
SDTI
SDTO
SMUTE
DEM0
DEM1
MCKI
VD
DGND
/PD
CMODE
AOUTL
AOUTR
VCOM
I
I
I
I
I
-
-
I
I
I
I
I
O
I
I
I
I
-
-
I
I
O
O
O
Positive voltage reference input , VA
Used as a positive voltage reference by
ADC & DAC, VREFH is conne externally
to filtered VA.
Rch analog positive input
Rch analog negative input
Lch analog positive input
Lch analog negative input
Analog power supply
Analog ground
Audio data interface format
Input/Output channel clock
Audio serial data clock
Audio serial data input
Audio serial data output
Soft mute
When this pin goes "H", soft mute cycle
is intiated.
When returning "L", the output mute releases.
De-emphasis frequency select
Master clock Input/X'tal input
Digital power supply
Digital ground
Reset
Master clock select (Internal biased pin)
"H": 384fs, "L": 256fs, "NS": 512fs
Lch analog output
Rch analog output
Common voltage output , VA/2
AK4522VF-E2 (XW008A00) CODEC (CMOS A/D & D/A Converter)
DSP-SPX: IC108, IC308