Yamaha Digital Sound Projector YSP-3000, Руководство по обслуживанию

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57
YSP-3000/YSP-30D/HTY-7030
YSP-3000/YSP-30D/
HTY-7030
SPI0, I2C0 and I2C1 serial port pins
Clocks
Device reset
Emulation/JTAG port
Power pins
AXR0[3]
AXR0[4]
AXR0[5]/SPI1_SCS
AXR0[6]/SPI1_ENA
AXR0[7]/SPI1_CLK
AXR0[8]/AXR1[5]/SPI1_SOMI
AXR0[9]/AXR1[4]/SPI1_SIMO
AXR0[10]/AXR1[3]
AXR0[11]/AXR1[2]
AXR0[12]/AXR1[1]
AXR0[13]/AXR1[0]
AXR0[14]/AXR2[1]
AXR0[15]/AXR2[0]
ACLKR0
AFSR0
ACLKX0
AHCLKR0/AHCLKR1
AFSX0
SPIO_ENA/I2C1-SDA
SPIO_CSC/I2C1-SCL
SPIO_CLK/I2C0-SCL
SPIO_SIMO
SPIO/SOMI/I2C0-SDA
CLKIN
OSCVSS
OSCIN
OSCOUT
OSCVDD
PLLHV
RESET
TMS
TRST
TDI
TDO
EMU[0]
EMU[1]
TCK
CVDD
Pin
No.
Function Name Detail of Function
117
119
120
121
122
126
127
130
131
134
135
137
138
139
141
142
143
144
105
107
108
110
111
17
22
23
24
25
27
14
19
21
28
29
32
34
35
8
16
20
33
44
53
57
65
77
85
90
101
123
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
PWR
I
O
PWR
PWR
I
I
I
I
OZ
I/O
I/O
I
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
IPU
IPD
IPU
IPU
IPU
IPU
IPU
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
N
N
N
N
N
N
McASP0 serial data 3
McASP0 serial data 4
McASP0 serial data 5 or SPI1 slave chip select
McASP0 serial data 6 or SPI1 enable (Ready)
McASP0 serial data 7 or SPI1 serial clock
McASP0 serial data 8 or McASP1 serial data 5 or SPI1 data pin slave out master in
McASP0 serial data 9 or McASP1 serial data 4 or SPI1 data pin slave in master out
McASP0 serial data 10 or McASP1 serial data 3
McASP0 serial data 11 or McASP1 serial data 2
McASP0 serial data 12 or McASP1 serial data 1
McASP0 serial data 13 or McASP1 serial data 0
McASP0 serial data 14 or McASP2 serial data 1
McASP0 serial data 15 or McASP2 serial data 0
McASP0 receive bit clock
McASP0 receive frame sync (L/R clock)
McASP0 transmit bit clock
McASP0 and McASP1 receive master clock
McASP0 transmit frame sync (L/R clock)
SPI0 enable (Ready) or I2C1 serial data
SPI0 slave chip select or I2C1 serial clock
SPI0 serial clock or I2C0 serial clock
SPI0 data pin slave in master out
SPI0 data pin slave out master in or I2C0 serial data
Alternate clock input (3.3 V LVCMOS input)
oscillator Vss tap point (for filter only)
1.2 V oscillator input
1.2 V oscillator output (No connected.)
oscillator 1.2 V VDD tap point (for filter only)
PLL 3.3 V supply input (requires external filter)
Device reset pin
Test mode select
Test reset
Test data in
Test data out
Emulation pin 0
Emulation pin 1
Test clock
Core supply
TYPE
(1)
PULL
(2)
GPIO
(3)
I/O