CDR-S1000
CDR-S1000
14
■
IC DATA
IC5 : HD64F3039F18
CPU
NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PORT
PB0
PB1
PB2
PB3
PB4
PB5
MD2
PB7
TXD0
RXD0
/IRQ4
VSS
D0
D1
D2
D3
D4
D5
D6
D7
VCC
A0
A1
A2
A3
Name
N_DEV_RST
MUTE
DIP0
LED0
FL_SCK
FL_DATA
MD2
FL_N_CS
TXD0
RXD0
N_IRQ4
VSS
D0
D1
D2
D3
D4
D5
D6
D7
VCC
A0
A1
A2
A3
I/O
O
O
I
O
O
O
I
O
O
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
Function
Resetting peripheral devices
Muting output
DIP SW data
Operation check LED
Clock for FL driver control
Data for FL driver control
Setting CPU operation mode
Chip select for FL driver control
SCI0 output
SCI0 input
External interrupt (Blank)
GND
Data bus
Data bus
Data bus
Data bus
Data bus
Data bus
Data bus
Data bus
+ 5V power
Address bus
Address bus
Address bus
Address bus
A17/P51
A16/P50
A15/P27
A14/P26
A13/P25
A12/P24
A11/P23
A10/P22
A9/P21
A8/P20
VSS
A7/P17
A6/P16
A5/P15
A4/P14
A3/P13
A2/P12
A1/P11
A0/P10
VCC
P71/AN1
P70/AN0
A
VSS
RESO/FWE
P65/WR
P64/RD
P63/AS
VCC
XT
AL
EXT
AL
VSS
NMI
RES
STBY
Ø
MD1
MD0
P60/W
AIT
P53/A19
P52/A18
TIOCA3/TP8/PB0
TIOCA3/TP9/PB1
TIOCA4/TP10/PB2
TIOCB4/TP11/PB3
T
O
CXA4/TP12/PB4
T
O
CXB4/TP13/PB5
MD2
ADTRG/TP15/PB7
TXD0/P90
RXD0/P92
IRQ4/SCK0/P94
VSS
D0/P30
D1/P31
D2/P32
D3/P33
D4/P34
D5/P35
D6/P36
D7/P37
P72/AN2
P73/AN3
P74/AN4
P75/AN5
P76/AN6
P77/AN7
AVCC
P80/IRQ0
P81/IRQ1
P91/TXD1
P93/RXD1
P95/SCK1/IRQ5
PA0/TP0/TCLKA
PA1/TP1/TCLKB
PA2/TP2/TIOCA0/TCLKC
PA3/TP3/TIOCB0/TCLKD
A23/PA4/TP4/TIOCA1
A22/PA5/TP5/TIOCB1
A21/PA6/TP6/TIOCA2
A20/PA7/TP7/TIOCB2
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
Содержание CDR-S1000
Страница 4: ...CDR S1000 CDR S1000 REAR PANELS 3 U C models A model B G models ...
Страница 48: ...CDR S1000 CDR S1000 ...